VINAY KUMAR RAYI

**** ****** ***** *****, ******, California 94560

www.linkedin.com/in/vinaysamuelr ac1rpn@r.postjobfree.com +1-408-***-****

OBJECTIVE

Seeking a challenging position in the field of electrical engineering which fully utilizes my skills and knowledge.

EDUCATION

Master of Engineering, Electrical Engineering (VLSI), University of Cincinnati, OH (Aug2015-Present) GPA - 3.3/4.0

Master of Technology in VLSI Designing, GITAM University, AP, India (2014) GPA - 8.97/10

Bachelor of Engineering, Electronics and Communications, Andhra University, AP, India (2011) 1st Class

Key Courses : VLSI Design Automation, VLSI Design for Test & Power, Intro to VLSI Design, Computer Architecture, Analog IC Design, Micro Fab Semi Conductor Devices.

TECHNICAL SKILLS

HDL: Verilog, VHDL, System Verilog (OVM & UVM methodologies).

Scripting: Perl.

EDA Tools: Cadence RTL compiler, Synopsys Design compiler, IC compiler, TetraMax, DFT, BSD.

Programming Languages: C, C++.

Others: HSPICE, IRSIM, Magic Layout Editor, Matlab, Modelsim, Xilinx, Linux.

ACADEMIC PROJECTS

Design of N-bit Array sorter, Chip sent to fabrication(MOSIS):

Designed a N-4bit array sorter (N=10) onto a chip. Logic simulation was done using Model-sim (VHDL coding-RTL and Gate level). Layout design using MAGIC and Simulations were performed for logic testing using HSPICE and IRSIM.

Technology: AMI C5 0.5 n-well process, 38 bidirectional pins, feature size 0.6u, Freq:85MHz.

CAD Tools in C++:

Net-list Bi-Partitioning Tool in C++:

Implemented the Kernighan-Lee algorithm for two-way partitioning of large number of cells. Code was successfully tested against heavy benchmarks consisting of 50,000 cells and 500,000 nets.

Placement and Routing tool in C++:

Implemented force-directed algorithm in C++ to achieve optimal cell placement, with help of total wire length estimate.

Lee’s maze routing algorithm was implemented to route these placed cells. Code was successfully tested against heavy benchmarks consisting of 1000 cells and 1000 nets.

Power Estimation(HSPICE):

Designed a low power inverter gate using Magic and analyzed its performance and power consumption using HSPICE.

Design and test of GCD calculator (Design Compiler, IC Compiler, TetraMax):

Developed GCD in Verilog design and synthesized using DC compiler. The design was tested using the test patterns generated by TetraMax ATPG. Scan chain insertion using DFT and boundary scan chain insertion using BSD Compiler. (Test patterns: 78, Fault Coverage: 95.82%)

Placing and routing using Synopsys IC compiler.

Logic Synthesis using (Cadence encounter RTL compiler):

Synthesize the gate level netlist for 8-bit accumulator with a behavioral netlist using standard cell library

Placement and routing of the synthesized gate-level netlist using standard cells.

Dual-Level power estimation and Gate level power optimization:

Estimated the power consumption of GCD calculator using power compiler and SAIF information. Power consumption was reduced by net switching activity reduction and pin swapping.

Performance analysis of a 32-bit multiplier using CLA and CSLA (Verilog/VHDL):

Design and implementation of two 32-bit unsigned number multiplication in VHDL using proposed CLA and CSLA adders which improved the overall performance of the multiplier.

Design of a Micro power low voltage multiplier, with reduced spurious switching (VHDL):

Design of a micro power 16x16 bit multiplier in VHDL for low voltage, power critical low speed applications. The micro power operation was obtained by reducing the spurious switching in the adder blocks of the multiplier.

HONORS

2014: Ranked 1st among all the master students in the VLSI design department, Gitam University.

2015: University graduate Scholarship, for best academic performance, University of Cincinnati.

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