Physical Design engineer

Adarsha Balaji

ac1tk4@r.postjobfree.com +1-267-***-****

**** ****** ***** ***** **** CA USA 94306

Education Master of Science, Computer Engineering GPA 3.40 Drexel University, Philadelphia, PA, June 2017

Concentration: ASIC Design and Computer Architecture Bachelor of Science, Telecommunication Engineering 72/100 Bangalore Institute of Technology, Bangalore, Karnataka, June 2012 Professional

Experience

Research Student Fall 2015 - Present

VLSI and Architecture Lab, Drexel University

Advisor : Dr. Baris Taskin

Synthesis of the ARM Cortex M0 benchmark with 32nm ARM libraries.

Synthesis of the OpenSPARC T1 FPU and design of a custom 4 FPU module with Synopsys 90nm libraries.

Floor planning, core utilization, clocking and powering schemes; fixation of timing violations using CTS models.

Static timing analysis; delay insertion and ECO changes for timing closure.

Low power configurations (power gating, multi-voltage domains).

Custom stack processor IP design and implementation based Xilinx ZYNQ architecture and using Xilinx Vivado design suite.

Design of a 64x32 Static Random Access Memory operating at 1.8GHz.

Skill scripting to automate layout generation and circuit scaling.

Work load profiling of multi-core NoCs - cluster traces using machine learning algorithms like K-means and bayesian hierarchical clustering.

Power and performance analysis of Multi-core applications. Senior Software Engineer June 2012 - June 2015

Robert Bosch Gmbh

Embedded C programming of CAN and Flex-ray transceivers and driver .

C++ and perl based Simulator (using Windows COM IPC) with multi-core embedded system simulation and RTOS behavior emulation.

RTL design of development transceivers for CAN drivers using a Xilinx-ZYNQ FPGA board.

TCP/IP and UDP module simulation development for Bosch AUTOSAR. Graduate Level

Coursework

ASICDesign I/II, CMOS VLSI Design, CustomVLSI Design, Parallel Computer Archi- tecture, High Performance Computer Architecture, Parallel Programming, Operating Systems, Digital Systems Design, Machine Learning, Fundamental of Systems I/II. Computer

Skills

ASIC Software: Encounter, Virtuoso, PrimeTime, Spectre, Synopsys DCC and ICC, Assura, Xilinx Vivado.

Languages: Skill, TCL, RTL, VHDL, Verilog, SystemC, SystemVerilog, Perl, Python, C, C++, CUDA, MPI, OpenMP, Pthread, Bash, Matlab. Computer Architecture Software and Compilers: GNU (gcc, g++, gdb, gcov), Gem5, Valgrind, Windows-COM, Git.

Network Protocols: PCIe, Wi-Fi, CAN, Flex-ray, LIN, TCP/IP and UDP. Architectures: ARM Cortex A-8, Intel x86, MIPS, Intel SSE, Kepler. References Dr. Baris Taskin, Professor, ECE Department, Drexel University.

Contact this candidate