Masters of Science

Madhuri Manjunath

*** **** ***, *** ****, CA-****4 832-***-**** ac1ruf@r.postjobfree.com www.linkedin.com/in/madhurimrao

Objective

Graduate student looking for challenging opportunities in the field of ASIC/Physical design, Process Integration.

Education

MASTERS IN ELECTRICAL ENGIEERING (THESIS) MAY 2017 UNIVERSITY OF HOUSTON

GPA: 3.85/4

BACHELORS IN ELECTRONICS AND COMMUNICATION ENGINEERING JUNE 2015 VTU, INDIA

GPA: 3.8/4

Technical Skills

Programming: C, MATLAB, Verilog, VHDL, Python, Perl, Tcl.

Software: Cadence Virtuoso, Cadence Schematic Entry, Cadence Layout Suite, LTSpice, Silvaco, Calp, Keil, Xilinx, Solid edge, Solid works.

Academic Projects

Thesis project: Fabrication of multichannel electrodes on optical fiber substrate. Jan 2016- May 2017

Patterning of 72 electrodes on a 330µm optical fiber substrate for optogenetic interrogation of neural circuits. Techniques and processes: D.C. magnetron sputter deposition, Neutral/Ion beam lithography, PECVD.

Semiconductor Processing Laboratory: Spring 2016

Hands-On experience in fabrication of Silicon wafer of desired thickness.

Performed Oxidation, Diffusion, Lithography, Etching and Wafer Cleaning in a class 100 clean room environment to fabricate and test Silicon Wafer of desired properties.

Relevant Coursework: VLSI Design, IC Engineering, CMOS Analog Integrated Circuit, Advanced Process Integration VLSI, Scanning Electron Microscopy, Optical Fiber Communication, Nanotechnology.

Cadence project on Operational Amplifier, and Common Source Amplifier Fall 2015

Designed an Operational Amplifier and Common Source Amplifier using 0.6µm technology in Cadence Virtuoso.

LVS and DRC checks were performed for the same.

Design of a 16-BIT SRAM: Fall 2015

Designed a 16 bit SRAM memory including the Sense Amplifier and the Pre-Charge Circuitry using 0.6um technology in Cadence Virtuoso. Sized the transistors, designed the Layout using Cadence Virtuoso Layout Suite and optimized the performance of the SRAM also verified the netlists using LVS. Verified result using PSpice simulations.

Analysis is done to determine sizes of all 6 transistors in a single bit cell for efficient Read/Write.

Optimized 16-bit row decoder with pre-decoding.

Optimized area*power*delay

Experience

RESEARCH ASSISTANT UNIVERSITY OF HOUSTON JAN 2016 – PRESENT

Dr. John. C. Wolfe’s group at the University of Houston working on microfabrication and operations manager for Leo 1525” High Resolution Scanning Electron Microscope.

Designing and developing a novel invasive type neural probe which attempts to address the crucial challenge of long term reliability and spatial resolution of neural implants with application in neuro-prosthetic devices.

INTERN VINYA’S INNOVATIVE TECHNOLOGIES, INDIA JULY 2014

Industrial familiarization at Vinya’s Innovative Technologies - provider of complete manufacturing services ranging from Printed Circuit Assembly to Complete System Integration and Box Build.

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