Design Test

Naveen Kumar Maddineni

**** ********* ***, ******** ****, CA 94043 Mobile: 408-***-****

https://www.linkedin.com/in/naveen2393 Email: **********@*****.*** OBJECTIVE

Seeking Full time opportunities in the field of Digital IP/SoC/Physical Design and Verification EDUCATION

Masters in Electrical & Computer Engineering GPA: 3.74/4.00 Aug 2015-April 2017 University of Florida, Gainesville, Florida

Bachelors in Electronics and Communication Engineering GPA: 84.1/100.0 Aug 2011-May 2015 Jawaharlal Nehru Technological University, Hyderabad, India

Graduate Courses: VLSI Circuits and Technology, Advanced VLSI Design, Computer Architecture, Advanced Data Structures, Parallel Computer Architecture, RTL/FPGA Design, Mixed Signal IC Test WORK EXPERIENCE

Technical Intern (IoT Team), Renesas Electronics ( Santa Clara, CA ) July 2017- Present

Developed python script to parse the Verilog netlist file and return total number of modules in Topcell hierarchy Circuit Simulation R&D intern Intern, Ansys ( Concord, MA ) Jan 2017- April 2017

Created component libraries for different Vendor components in Nexxim circuit simulator of ANSYS Electronics Desktop (AEDT 18.2) and Completed the testing of Nexxim support for different Vendor MOSFET models

Scripting in Python to automate the built of library files from datasheet and to check for the parser errors in Simulator

Created Test cases for Nexxim QA test suite to implement daily regression testing

Worked on Agile framework to verify the code changes for the BSIM3 model in Pspice Tools: Ansys Electronics Desktop (Circuit, SIwave), LTSpice, PSpice, MATLAB, CA Agile Languages: Python TECHNICAL SKILLS:

Areas: ASIC, FPGA, Computer Architecture

RTL design using Verilog HDL, Synthesis and Static timing analysis

Timing violations analysis and compensating techniques

Programming Languages: VHDL, Verilog, C, C++, Python, Embedded C, Assembly, MPI, OpenMP, LabVIEW

Tools: Cadence (Spectre, Vituoso, SOC Encounter, ICFB), Synopsys Design Compiler, ModelSim, Xilinx Vivado/ISE, TINA-TI, Aldec Active-HDL, Eclipse, PyCharm, Unix/Linux, National Instruments (Savage Tester, Test Stand) PROJECTS

Optimum Cache Design using MNM Techniques for Alpha 21264 processor [ C, SimpleScalar ]

• Implemented Mostly No Machine technique on multi-level cache architecture to detect a cache miss even before searching the entire cache & redirect the reference to next cache level on a miss, thereby improving the memory performance

Hash Tag Counter (Advanced Data Structures) [ C++]

• Implemented a system to find “n” most popular hash tags, that were given through the input file by using Max Fibonacci heap and Hash table data structures and ran it for 100,000 nodes

32-bit low power MIPS Processor at 180nm from RTL to GDSII [ ModelSim, Synopsys Design Compiler, Cadence Encounter ]

• Designed a 32-bit low power 600MHz five stage pipelined MIPS processor at 180nm technology node using VHDL

• Achieved 52% power reduction by using clock gating Design Rule Checking (DRC) and LVS constraints are met

Custom 8X4 6T SRAM Cell Design in 250nm Technology [ Cadence Schematic Composer, Spectre, Virtuoso ]

• Designed 8x4 SRAM array with optimal sizing by adjusting cell-ratio(CR) and pull-up(PR) ratio in 250nm CMOS technology

• DRC, LVS are verified using divaDRC and divaLVS rules

Pipelined 1-D Time domain convolution on Xilinx Zedboard [ VHDL, Xilinx Vivado, Zedboard Zynq-7000]

• Designed a custom circuit on FPGA that performs 1D Time Domain convolution in multiple clock domains and verified it using C++ test bench. Programmed VHDL code for smart and kernel buffers to utilize maximum memory bandwidth

• Implemented handshake and dual flop synchronizers to enable clock domain crossing and prevent metastability

Mixed Signal IC Test Lab Projects

• Developed automated test sequences using NI TestStand for testing Texas Instruments IC’s like LDO, OPA277, TMP 20, TMP 175 on NI Automated Test Equipment.

• Integrated LABVIEW code modules with NI Teststand to verify various test parameters of the Device Under Test.

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