| Resume alert | Resumes 121 - 130 of 448 |
Design Engineer
San Jose, CA, 95126
... SKILLS Languages Verilog, System Verilog, UVM (Universal Verification Methodology), C/C++, Perl(Learning), PLC & SCADA. Testing Skills SCAN, ATPG, BIST, RTL design, Simulation, Synthesis and Debugging, Static and Dynamic Timing Analysis. Tools ... - 2017 Oct 05
... SKILLS Languages Verilog, System Verilog, UVM (Universal Verification Methodology), C/C++, Perl(Learning), PLC & SCADA. Testing Skills SCAN, ATPG, BIST, RTL design, Simulation, Synthesis and Debugging, Static and Dynamic Timing Analysis. Tools ... - 2017 Oct 05
Electrical Engineer
San Jose, CA
... used Verilog (Model/Questa Sim), Python(Spyder), UVM Completed 9+ projects utilizing Verilog, SystemVerilog, Virtuoso, VCS, NC-Verilog, Quartus Prime, ModelSim 3.855 GPA, concentration in ASIC / Digital System/Logic/CMOS-IC / SoC Design / ... - 2017 Oct 02
... used Verilog (Model/Questa Sim), Python(Spyder), UVM Completed 9+ projects utilizing Verilog, SystemVerilog, Virtuoso, VCS, NC-Verilog, Quartus Prime, ModelSim 3.855 GPA, concentration in ASIC / Digital System/Logic/CMOS-IC / SoC Design / ... - 2017 Oct 02
Sr/Staff Electrical Engineer(FPGA)
Sunnyvale, CA
... in Electrical Engineering, 1991 – 1995 Overall GPA: 3.15/4.0 SKILLS Languages: Verilog, Python, Blueprint RDL, Assembly, C. Tools: Xilinx ISE, Xilinx Vivado, Xilinx SDK, Chipscope, ModelSim, NCVerilog, ConceptHDL, Allegro PCB Viewer, Protel, ... - 2017 Oct 02
... in Electrical Engineering, 1991 – 1995 Overall GPA: 3.15/4.0 SKILLS Languages: Verilog, Python, Blueprint RDL, Assembly, C. Tools: Xilinx ISE, Xilinx Vivado, Xilinx SDK, Chipscope, ModelSim, NCVerilog, ConceptHDL, Allegro PCB Viewer, Protel, ... - 2017 Oct 02
Electrical Engineering Graduate Student
San Jose, CA, 95129
... 2015 Bachelor of Science in Electrical Engineering (Embedded Systems), Cum GPA: 3.57, Major GPA: 3.67 SKILLS • Languages: Java, Python, C, Verilog, Assembly. • Other: Android Studio, Open CV, FPGA, Mac OS X, Linux, Matlab, SciKitLearn, NLTK. ... - 2017 Sep 28
... 2015 Bachelor of Science in Electrical Engineering (Embedded Systems), Cum GPA: 3.57, Major GPA: 3.67 SKILLS • Languages: Java, Python, C, Verilog, Assembly. • Other: Android Studio, Open CV, FPGA, Mac OS X, Linux, Matlab, SciKitLearn, NLTK. ... - 2017 Sep 28
Design Engineer Information Technology
San Jose, CA
... TECHNICAL SKILLS • Programming Languages Verilog, C, C++, OpenMP, MPI, Cuda, Perl, Matlab, Python, Assembly (8086). • Tools used Virtex 6/7 FPGA, Synplify, Xilinx ISE, VCS, Caffe, Nvidia Jetson TK1, Protolink. • Key Skills Problem Solving, RTL ... - 2017 Sep 23
... TECHNICAL SKILLS • Programming Languages Verilog, C, C++, OpenMP, MPI, Cuda, Perl, Matlab, Python, Assembly (8086). • Tools used Virtex 6/7 FPGA, Synplify, Xilinx ISE, VCS, Caffe, Nvidia Jetson TK1, Protolink. • Key Skills Problem Solving, RTL ... - 2017 Sep 23
Electrical Engineering
San Jose, CA
... Languages: C, Python, Verilog. CERTIFICATIONS: In progress: CCNA certification. EXPERIENCE: Summer Intern - 6Connect Jun 2017 – Aug 2017 Worked on Visualization techniques for IPv6 addresses and UI tool of 6Connect ProVision network automation and ... - 2017 Sep 22
... Languages: C, Python, Verilog. CERTIFICATIONS: In progress: CCNA certification. EXPERIENCE: Summer Intern - 6Connect Jun 2017 – Aug 2017 Worked on Visualization techniques for IPv6 addresses and UI tool of 6Connect ProVision network automation and ... - 2017 Sep 22
ASIC Design and Verification/ Physical Design and Layout
Fremont, CA
... TECHNICAL SKILLS Programming Languages: C, C++, Java/J2EE, Oracle, Perl, Python, Verilog HDL, System Verilog, UVM. Design Tools: Matlab/Simulink, Xilinx ISE, Synopsys (Design Compiler), Design Vision, Altera Quartus II, ModelSim, PSPICE, Cadence ... - 2017 Sep 20
... TECHNICAL SKILLS Programming Languages: C, C++, Java/J2EE, Oracle, Perl, Python, Verilog HDL, System Verilog, UVM. Design Tools: Matlab/Simulink, Xilinx ISE, Synopsys (Design Compiler), Design Vision, Altera Quartus II, ModelSim, PSPICE, Cadence ... - 2017 Sep 20
Design Engineer Software
San Jose, CA
... Languages & Version Control: Verilog, C, Perl, SystemVerilog & C++, GIT, P4, CVS, SVN. Employment Details: S.no Organization Period Position 1 ESENCIA Technologies May 2016 - till date Staff Design Engineer 2 Soft Machines April 2013 – April 2016 ... - 2017 Sep 20
... Languages & Version Control: Verilog, C, Perl, SystemVerilog & C++, GIT, P4, CVS, SVN. Employment Details: S.no Organization Period Position 1 ESENCIA Technologies May 2016 - till date Staff Design Engineer 2 Soft Machines April 2013 – April 2016 ... - 2017 Sep 20
Junior ASIC Design Engineer
San Jose, CA, 95112
... Technical Background: o Skills: ASIC RTL Design, Digital Logic Design, Test-Bench Development, Assertions, Simulation, Synthesis, Static Timing Analysis, Computer Architecture, Debug, Functional and Code Coverage o Languages: Verilog HDL, System ... - 2017 Aug 30
... Technical Background: o Skills: ASIC RTL Design, Digital Logic Design, Test-Bench Development, Assertions, Simulation, Synthesis, Static Timing Analysis, Computer Architecture, Debug, Functional and Code Coverage o Languages: Verilog HDL, System ... - 2017 Aug 30
Electrical Engineer
San Jose, CA
... Processing Electronic Device SKILLS Cadence, P-Spice (OrCad), knowledge of Matlab, C/C++, Java, ARM, knowledge of MIPS, Verilog, Microsoft Office, Microsoft Project, Keil uVision 4, experience in Linux, FPGA Design and implementation, Xilinx, VHDL ... - 2017 Aug 30
... Processing Electronic Device SKILLS Cadence, P-Spice (OrCad), knowledge of Matlab, C/C++, Java, ARM, knowledge of MIPS, Verilog, Microsoft Office, Microsoft Project, Keil uVision 4, experience in Linux, FPGA Design and implementation, Xilinx, VHDL ... - 2017 Aug 30