SUNIL BHAUSAHEB DABHADE

#****, ****** *********, *** **** Street, San Jose, CA -95126. +1-669-***-****, ac2lt0@r.postjobfree.com EDUCATION Master in Electrical Engineering, specialization VLSI/ASIC design. San Jose State University, San Jose, CA, USA. May 2017. Related Courses - Digital System Design and Synthesis, Principles of Semiconductor Devices, Computer Architecture, CMOS ASIC Design, FPGA DSP System Design, SoC Design and Verification, Digital System Verification, Universal Verification Methodology. Bachelor of Engineering (B.E.) in Electronics, Mumbai University, Maharashtra, India. July 2012. SKILLS Languages Verilog, System Verilog, UVM (Universal Verification Methodology), C/C++, Perl(Learning), PLC & SCADA. Testing Skills SCAN, ATPG, BIST, RTL design, Simulation, Synthesis and Debugging, Static and Dynamic Timing Analysis. Tools Xilinx ISE, Modelsim, Vivado, SDK, Quartus, eclipse, Synopsys VCS, Design Compiler, GTK Wave, Eagle, Rslogix 500, Keil, Matlab, Multisim, Protel SE.

Device ZC706 (xc7z030fbg676-3), Altera development kit - DE1. Protocols SOC bus protocol AHB, APB, SPI, PC/AT, PCI, AXI. EXPERIENCE LeWiz Communications, Inc. October 2016 – May 2017. Responsibility: Hardware Design Engineer (Intern)

• Developed code for Lewiz Xilinx FPGA Board. Wrote server acceptance state machine code for TCP/IP offload engine. Simulated with Vivado ISE Xilinx tools. Modified existing ZYNQ FPGA code to allow the testing the functionality of an FPGA board which is involving Verilog and C code.

• Involved in the extensive testing, verification, and board bring up for the Zynq ZC30. Defining detailed test plan and writing test bench to cover testcases to verify design functionality.

• Performed Simulation on the Company's IP and made the changes to the FIFO blocks in the design. Integrated various IP cores

(LogicCore) of SDRAMs, FIFO controllers with other logic. Converted Altera’s constraints file (SDC) into Xilinx constraints file (XDC). Also, familiar with UCF constraints file.

• Integrating various level complex design modules with other design and converting a design into the Parameterizable design for reusability of code.

Sonodyne International PVT LTD. July 2013 – June 2014. Responsibility: Production Engineer.

• Performed Electrical testing & rectification of power supply models like FSP (Fixed Switch Mode Power Supply), VSP (Variable Switch Mode Power Supply), VLP (Variable Linear Power Supply).

• Tested amplifier models which include AMIS (Australian Monitor Installation Series)-AMC, MX(Mixer) series.

• Involved in the manual fabrication of PCB’s. Also, proficient in soldering of SMD components. PROJECTS BUS Arbitration (RTL design using Verilog)

• Designed and simulated the priority based bus arbitration for four Masters and four Slaves using Synopsys VCS.

• It was mainly depended on “bidding” methodology of arbitration to choose appropriate master and slave. CRC Block Design

• Designed the CRC Block generator with implementation of reverse logic, LFSR generators and synthesized the design using VCS Synopsys at 300 Mhz.

Box Muller theorem

• Implemented the Box- Muller transform in Verilog to convert two random numbers to an approximation of a Gaussian random number distribution. The design was pipelined to run at 220 MHz using Synopsys VCS tool. Designed of 64-bit High Speed adders

• Implemented, Optimized and Analysed performance of four different implementations of 64-bit adder for Power, Timing, Area.

• Ripple-Carry-Adder (RCA), Carry-Look-Ahead (CLA-2L) with 4-bit groups and 2-level P-G generator, Carry Selected Adder

(CSA-EQG) with 4-bit groups, Carry Selected Adder (CSA-UEQG) with unequal-bit groups for highest speedup. Performed simulation and synthesis using Synopsys VCS.

Floating point multiplier

• Implemented floating point multiplier RTL design in Verilog using Synopsys VCS tool. It was working at 20 MHz Redesigned it with pipeline concept to work at 300 MHz. Also, implemented this project using Altera Quartus II tool. UVM Based AXI4-Lite Code Coverage (System Verilog, UVM)

• Design for the AXI4-Lite Master bus was developed using Xilinx Vivado. After the design part, Verification test bench was developed using UVM (System Verilog).

• Coverage script and the test cases were driven to find various coverage matrices like line, conditional and FSM matrices. DSP MAC with rounding and saturation logic

• Implemented multiply and accumulate (MAC) circuit using Altera Mega Wizard with rounding and saturation logic. ACTIVITIES AND AWARDS_

• Worked as a Treasurer in EESA 2010-11. Organized and lead various events at undergraduate. Completed Robotics Workshop

(wired) conducted by the IEEE students chapter of KJSIEIT on 07/02/09. Participated in the Typhoon(Robotics) event stood 2nd conducted by the IEEE students chapter of KJSIEIT on 18/09/09. Participated in interschool / intercollege Cricket tournaments.

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