Design Engineer Software

RESUME

PERSONAL PROFILE:

Name : RajashekharReddy Beeram Mobile Num : +1-669-***-****

Email ID : ac2dt7@r.postjobfree.com Date of Birth : 3rd Aug-1980

Location : SanJose, CA

EXECUTIVE SUMMARY:

Experience Summary: Having 14+ years of Experience in SOC DFx SCAN, EDT & ATPG and MBIST and LBIST implementation and verification, Virage memory compilers, RTL Design & verification for multiple IP’s and interfaces ( IEEE 1149.1 & IEEE 1394b), FPGA (Xilinx) based RTL designs, synthesis & implementation and validation of FPGA.

Skills/Tools:

Core Exposure: dft SCAN, EDT and ATPG generation, MBIST, FPGA synthesis & pnr, ASIC validation on FPGA Board, FPGA prototyping, Basics on ASIC synthesis,linting. ASIC and IP level RTL design and verification for multiple IP’s and interfaces.

Domain Expertise: DFT JTAG & P1500 interface, SCAN,BSCAN, MBIST, XILINX FPGAs, IEEE 1394b & IEEE 1149.1s, AHB, PCI interface & I2C & WUSB.

Memory Compiler & DFT tools: Synopsys DftCompiler, TetraMax, si_debug, Mentor TestKompressor, Virage memory Compiler, LV, Virage verifier & pattern generation, STAR yields accelerator, JTV tool, VCS, Verdi, Simvision, ncVerilog

Synthesis, Simulation and Debugging Tools: XILINX, Synplify Pro & Premier & Certify for FPGA, knowledge on RC, DC & spyglass linting, ChipScope, Signal Tap and Logic Analyzer, Oscilloscope.

Languages & Version Control: Verilog, C, Perl, SystemVerilog & C++, GIT, P4, CVS, SVN.

Employment Details:

S.no

Organization

Period

Position

1

ESENCIA Technologies

May 2016 - till date

Staff Design Engineer

2

Soft Machines

April 2013 – April 2016

Senior AsicDesignEngineer-2

3

AMD

May 2008 – November 2012

ASIC design Engineer-2

4

Wipro Technologies

November 2005 –April 2008

Senior software Engineer

5

SigmaMicroSystems Pvt Ltd

August 2002 – October 2005

Design Engineer

MOST-RECENT Degree Type:

Bachelor of Technology in Electronics Communication Engineering from JNTU, in April 2002.

WORK EXPERIENCE:

Organization : INTEL (Employer ESENCIA TECH)

Projects : IVCAM2.0-MA, IVCAM2.0-MC, PCIe_SS_TC

Tools used : Synopsys dft compiler & TetraMax, VCS, git, Si_debug, DC compiler, Tcl

Roles & Responsibilities: Involved in SCAN insertion and ATPG generation at block level and top level with Synopsys tools, OCC logic insertion, ATPG pattern generation and simulation with zero delay, max and min timing, BSCAN simulation, MBIST pattern generation and simulation.

Organization : Soft Machines (SMSilicon)

Projects : Mojavi SOC, Crater 16nm Test chip, WPU SOC

Tools used : TestKompress, LV, Modelsim, ncverilog, git, svn, Verilog, Tcl

Roles & Responsibilities: Involved in block level SCAN & EDT insertion, ATPG generation & simulation, Top level SOC scan & EDT insertion, MBIST insertion and simulation, BSCAN simulation. Implemented DfxController RTL logic and integrated with functional blocks, OCC logic implementation for atspeed scan. Verification of dfx control logic and occ logic. Involved in SOC chip bring ups on TESEDA tester.

Organization : Advanced Micro Devices (AMD)

Projects : KABENI for APU, SHASTHA & ARICIBO for game console

Tools used : VCS, Verdi, Verilog, SV, C++, Virage memory compiler, XILINX, SynplifyPro, SynplifyPremier, Certify

Roles & Responsibilities: Involved in integration of DFx dv logic from DFx IP to SOC level and SOC dft dv flow bring up, dv test plan and reviews. DFx functionality verification for legacy features and new features for JTAG, P1500, SCAN, ScanDump, MBIST, LBIST, PLL and other DFx features and RTL design changes for bug fixing. Generated different types of memories by using Virage memory compilers and memory wrappers, Technology Library maintenance which is delivered by technology vendor and basic checks for new library release. Involved in Basic Front End implementation activities synthesis with RC, DC compilers, linting and LEC for libraries.

FPGA synthesis for 2 FPGA board and Diag testing, full chip partition for 8 FPGA setup, synthesis and PAR.

Organization : WIPRO Technologies

Projects : OHCI Link interface, AVLink interface, IEEE STD 1394PHYB IP

Tools used : Verilog, simvision, ncverilog, Spyglass, Xilinx

Roles & Responsibilities: Involved in OHCI ip RTL design modifications, Errata fixes in RTL, RTL bug fixes, Verification of IP functionality with legacy TB and new test cases to verify bugs, IP validation on FPGA board, synthesis & implementation. RTL design for Interlace to progressive scan data conversion in NTSC/PAL standards as per IEC standard. Verification of IEEE1394b IP functionality with legacy TB and new testcases to verify bugs, RTL design modifications for better throughput, bug fixing, Errata updates in RTL and linting,

Organization : SIGMA MicroSystems

Projects : RTG, SER, PDWG, ARINC BI PHASE COMMUNICATION CARD, SYNCHRO/FREQUENCY GENERATOR,.

Tools used : Verilog, C, XILINX, PADS, Oscilloscope, LogicAnalizer.

Roles & Responsibilities: Involved in RTL design micro architecture and documentation, RTL design & verification in verilog, RTL design synthesis & implementation for FPGA programing, PCB board design and design validation PCB board. RTL design for pci interface, memory interface, design for packet data conversion for received serial data to 8bit parallel data frame and transmit parallel frame data to serial data, FIFO interface.

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