RACHIT GARG

**, *** ****** *, #**** ac2ftt@r.postjobfree.com

San Jose, CA 95134 +1-765-***-****

OBJECTIVE

To find an exciting full time role in the areas like Architecture, Performance Analysis, RTL Development, FPGA Design. EDUCATION

Purdue University, West Lafayette, IN

Master of Science, Electrical and Computer Engineering Aug 2013 - May 2016 Courses: SoC Design, Programming Parallel Machines, Computer Architecture, Data Mining GPA: 3.86/4.0

Indian Institute of Information Technology, Allahabad, India Bachelor of Technology (with Honors), Electronics and Communication Engineering Aug 2009 - June 2013 Awards: Institute Merit Scholarship, 2010

GPA: 9.29/10

PROFESSIONAL EXPERIENCE

Oracle Corp., Santa Clara, CA June 2016 – Present

Hardware Design Engineer

• Micro-architecture and RTL design of synthesizable bus functional model of memory controller from scratch.

• Wrote scenario/random tests in C/C++ to hit coverage goals and provided support for software development.

• Awards: SPARC Achievement Award

Qualcomm Inc., San Diego, CA May 2015 – August 2015 Hardware Design Intern

• Development of Power and Performance correlation content for various Networks on Chip on the latest Snapdragon chipsets across different frequency and bandwidth points.

• Developed a strategy for the first time to measure the dynamic power consumption of a clock tree. Freescale Semiconductor, India Design Center Jan 2013 - August 2014 Hardware Design Engineer

• Front End Integration of IP. Backend FPGA flow. Board bring-up on FPGA. Validation Plans and their Execution.

• Prototyping of flash memory controller(QSPI) with the fastest flash in the market- Spansion’s hyperflash interface.

• Awards: Team Bravo Award, Winning Starts Here Award.

• Conceptualized and set up a flow for guided regressions in the Pre Silicon FPGA environment. ACADEMIC PROJECTS

• Low Power Image Recognition Challenge: Co-organized LPIRC in Design Automation Conference – 2015 and proposed/ implemented optimization for low power implementation of inference in Convolutional Neural Nets on Caffe.

• Map Reduce: Implementation and analysis of Map Reduce algorithm for word count problem using OpenMP and MPI.

• Matrix Multiplication: Implementation and Evaluation of parallel matrix multiply algorithms in OpenMP/MPI.

• Cache Performance Analysis: Implementation and performance analysis of skewed associative caches and victim caches on gem5 simulator across different configurations.

• JPEG Decoder: Designing a custom SoC on Altera FPGA to speed up software implementation of Jpeg decoder. Used concepts like hardware/software partitioning, custom instructions, separate IP block, to obtain speedup of 10x.

• Wallace Tree Multiplier: Designed 3 stage unbalanced pipelined 8-Bit Wallace tree multiplier at the transistor level. TECHNICAL SKILLS

• Programming Languages Verilog, C, C++, OpenMP, MPI, Cuda, Perl, Matlab, Python, Assembly (8086).

• Tools used Virtex 6/7 FPGA, Synplify, Xilinx ISE, VCS, Caffe, Nvidia Jetson TK1, Protolink.

• Key Skills Problem Solving, RTL development, FPGA Development, Computer Architecture. PUBLICATIONS

• Rachit Garg, Gaurav Mishra, Neetesh Purohit and Vishal Kesari, “Three-element Circular Antenna-array with Beam Rotation Mechanism”, European Journal on Microwave Application, Cambridge University Journal, 2014.

• Vaze, R.; Garg, R.; Pathak, N., "Dynamic Power Allocation for Maximizing Throughput in Energy-Harvesting Communication System," Networking, IEEE/ACM Transactions on, vol.PP, no.99, pp.1,1, 0 doi: 10.1109/TNET.2013.2281196, 2013.

• Y.H. Lu et al., “Rebooting Computing and Low-Power Image Recognition Challenge”, International Conference On Computer Aided Design 2015.

AWARDS AND HONORS

• Awardee, “SPARC Achievement Award”, given by Oracle Leadership Team for owning multiple critical projects in parallel, 2017.

• Awardee, “Winning Starts Here” Award, given by Freescale Semiconductor Leadership Team for excellent execution of the project QSPI IP Validation, 2014.

• Awardee, “Team Bravo” Award, given by Freescale Semiconductor Leadership Team for Team work and high performance shown in pressure situations, 2014.

• Awardee, “Institute Merit Scholarship”, for being among top 5 students out of 200 in class, 2010.

• Ranked among top 10% students, National Standard Examination in Chemistry (NSEC) by Indian Association Of Physics Teachers (IAPT), 2009.

• Second Place, "RoboRace"- Robotic event in Effervescence, Annual Tech-fest, IIIT-Allahabad, 2010.

• Third Place, "Mangix"- Circuit Design Competition, Effervescence Annual Tech-fest, IIIT-Allahabad, 2010.

• Third Place, “Magnum Opus”- Software development Competition, Effervescence Annual Tech-fest, IIIT-Allahabad, 2011.

ADDITIONAL INVOLVEMENTS

• Organizer, EC Marathon, an electronics event, Effervescence, Annual Techfest, IIIT-Allahabad, 2011.

• Volunteer, 3rd Science Conclave, “A congregation of Nobel Laureates and Eminent Scientists” 2010.

• Volunteer, Prayaas, An initiative by students of IIIT Allahabad to teach underprivileged students of the city, 2012.

• Blogger on techno-philosophical issues -

www.idoodle.co.nr: Account of hobby experiments on MATLAB. www.searchingourselves91.blogspot.com: Posts on technical interpretation of philosophical issues.

Contact this candidate