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Portland, OR
... on ASIC/FPGA Chip and High Speed Digital & Analog Board Level Design SKILLS Design & Testing Tools: • HSPICE & PSPICE, VeriLog HDL, OVN/UVM System Verilog and VHDL • IBM PC XT/AT, Pentium, Pentium Pro Motherboard and I/O, PowerPC Architecture ...
- 2019 Jun 26
Vancouver, WA
... time constraints SKILLS • Experience with: o Simulation and design software such as Cadence PSpice and Ansys HFSS o Verilog, C, MATLAB, Visual Basic and Assembly programming o Cleanroom and ESD safe environments • Microsoft Office (Excel, Word ...
- 2019 Jun 20
Portland, OR
... Basic knowledge of VHDL and VERILOG design and implementation. Experience on real time OS (VxWorks/pSOS, Linux, Windows) and socket implementation. Experience with Quality Assurance tracking tools like HP QC, JIRA etc. Knowledge of Rational's Clear ...
- 2018 Dec 04
Portland, OR
... Neural Networks Digital IC Design Application Specific Integrated Circuits (ASIC) Microprocessor System Design Pre Silicon Functional Verification Technical Skills • RTL Design and Verification experience using Verilog, System Verilog and VHDL. ...
- 2018 Feb 12
Portland, OR
... (Sep’15-Jun’17) University of Pune, (Aug’11-Jun’15) TECHINCAL SKILLS Programming : SystemVerilog, SystemVerilog Assetions, Verilog, C,C++, Python, Assembly, MATLAB, Perl Tools : Synopsys DC, Design Vision, Questasim, Cadence Virtuoso, Vivado Other ...
- 2017 Nov 27
Portland, OR
... Institute of Technology, University of Mumbai, India (GPA: 3.65/4.0) KEY SKILLS ● Programming: Verilog, SystemVerilog, C/C++ ● Scripting: Tcl, Perl ● EDA Suite and Tools: Xilinx Vivado, Synopsys DC & ICC WORK EXPERIENCE Project Volunteer Intern, HDL ...
- 2017 Sep 23
Portland, OR
... SKILLS Language: C, C++, Java, Assembly, SQLite, Verilog, Python, Perl, Shell Scripting, OpenWRT, and Git. EDA tools: Code Composer Studio, Android Studio, Eclipse, Virtuoso, Vivado, Eclipse, Code Blocks. Expertise: RTL code, Debugging (JTAG & GDB), ...
- 2017 Aug 18
Beaverton, OR
... Master of Science in Electrical Engineering, Expected May 2017 SRM University, Chennai, TN, India Bachelor of Technology in Electronics and Communication Engineering May 2015 TECHNICAL SKILLS Hardware Descriptive Languages: RTL Verilog, VHDL; ...
- 2017 Jul 24
Hillsboro, OR
... 970-***-**** ac0b54@r.postjobfree.com https://www.linkedin.com/in/NishitKapadia (PhD in Electrical and Computer Engineering) SKILLSET Logic design: VHDL Verilog-HDL SystemVerilog ISE (Xilinx FPGAs) Design Compiler Modelsim VIS (formal verification) ...
- 2017 May 16
Beaverton, OR
VLSI Verification engineer with * years * months of professional work experience in ASIC verification using UVM & System verilog and 1 year 10 months as an Assistance Professor. Have excellent working knowledge of AHB protocol and SoC functional ...
- 2017 Mar 14