VLSI Verification engineer with * years * months of professional work experience in ASIC verification using UVM & System verilog and 1 year 10 months as an Assistance Professor. Have excellent working knowledge of AHB protocol and SoC functional Verification. Have Excellent Communication and Presentation skills and Good as Team Builder and team player and flexible to suit in any challenging environment.

Professional Summary

5 year 4 months of experience as ASIC Verification Engineer

SoC/ASIC Verification

Experience in the area of SoC functional verification and IP block verification using System Verilog & UVM

Functional verification experience at System level using HVL – System Verilog(SV)

Experienced in Triage and debugging at block level

Experienced in test plan development, test implementation, verification environment development, RTL simulations and verification Sign-off

Hands on experience in VHDL, Verilog, System Verilog, Running Regressions, Assertions, Toggle coverage, Functional Coverage, Test Plan and Test cases development

Under gone VLSI Design & Verification trainings includes HDL based Verification, System Verilog, Assertions, code coverage, Randomization and functional coverage

Worked on Verification of unit level Verification of SDC and SFP modules

Responsible for

Developed a complete UVM environment for Round-Robin arbiter.

Developed UVM sequences/scenarios for multiple modules.

Debugging the fails and fixing them as per specification documents.

Adding checkers/monitors as per the functionality.

Writing System-verilog assertions for the expected properties of Design.

Developing additional testcases based on Toggle coverage.

Documentation of detailed verification plans and for its reviews with design staff.

Running functional and Toggle coverage regressions and reporting to client.

Good Knowledge on Object Oriented Programming Concepts.

Technical Skills

Programming Languages : System Verilog, Verilog HDL, VHDL, Unix,

Methodologies : UVM

EDA tools : Synopsys, Mentor Graphics

Simulation tools : Synopsys-VCS, DVE,Model-sim

Protocols Known

AHB

SPI

Trainings and Certifications

Trained in System Verilog, Verilog, UNIX system programming.

Trained in PERL scripting language.

Experience Summary

Organization

Designation

Duration

FREESCALE SEMICONDUCTOR,USA

WIPRO Technologies, India

Project Engineer

Project Engineer

09/2016 – 01/2017

08/2011 – 07/2016

Sree Chaitanya College of Engineering, India

Asst. Professor

12/2007 – 09/2009

Project Profile#1: FREESCALE SEMICONDUCTOR (VERIFICATION)

Project Location: USA

VLSI Verification Engineer from 09/2016 to 01/2017

1. SPI Verification in UVM Methodology

Project Description:

This project involves development of UVM based environment for Verification of SPI protocol,

which has a single master and multi slave.

Contribution:

Created the test-plan with all the scenarios needed to test.

Coded the required environment in UVM based methodology, which involves drivers, monitors, scoreboard and sequencers.

Ported the sequences for all modes of SPI operation.

Collected the functional Coverage for few I/O signals and made sure that its 100%.

Project Profile#2: FREESCALE SEMICONDUCTOR (VERIFICATION)

Project Location: Wipro Technologies, India

VLSI Verification Engineer from 07/2014 to 06/2016

2.LS2080 ARM A57 based SoC Verification

Project Description:

This project involves porting of sequences in UVM, building/updating the environment by adding necessary components and checkers/scoreboards to meet the latest SoC functionality, Coding all the required environment and checkers and this is project based on ARM architecture.

Contribution:

As a team member responsible for Verification of Coresight Debug Architecture and Skyblue interface protocol.

Had to integrate the Skyblue IP level environment to SoC level for all IP’s.

Updating the Verification plan with all the possible scenarios and working based on these milestones.

Adding checkers to all the sequences to check the latest functionality.

Project Profile#3: FREESCALE SEMICONDUCTOR (SoC VERIFICATION)

Project Location: Wipro Technologies, India

VLSI Verification Engineer from 01/2014 to 06/2014

3.ARM based SoC Verification

Project Description:

Wipro Technologies has one of the valuable client Freescale; Freescale Semiconductor is the leading manufacturer of microcontrollers, microprocessors and semiconductors. The objective of the project was to develop & validate test cases in UVM (Universal Verification Modelling) for the blocks SFP (Secure Fuse Programming) and SDC (Secure Debug Controller), prepared verification plan and test case passing includes Regressions, Toggle coverage and Functional Coverage.

Contribution:

As a team member responsible for Verification of SFP and SDC modules.

Developed most of the checkers for the project execution (Clock monitors, assertions).

Created a test plan, which covers all the features according to the module specification.

Worked on creating functional coverage bins.

Developed Test cases and Unit testing

Prepared Verification plan for SFP and SDC blocks also includes Regressions, Toggle coverage and functional coverage

Run tests, triage & debugging and prepared summary

Project Profile#4: FREESCALE SEMICONDUCTOR (SoC VERIFICATION)

Project Location: Wipro Technologies, India

VLSI Verification Engineer from 06/2013 to 12/2013

4.Round Robin Arbiter Verification

Project Description:

Round robin arbiter arbitrates between multiple parameterized requests and issues grant in cyclic order. It blocks masked requests and sends unmasked requests to the arbiter logic block. The objective of the project was to develop the RTL code of Round robin Arbiter in Verilog and coverage driven constraint random verification (CRDV) in UVM. Validating the test cases and prepare verification plan.

Contribution:

As a team member responsible for Verification of the arbiter using UVM.

Created a test plan, which covers all the features according to the module specification.

Developed Test cases using coverage driven constraint random verification (CRDV).

Adding checkers to all the sequences to check the latest functionality.

Project Profile#5: FREESCALE SEMICONDUCTOR (VERIFICATION)

Project Location: Wipro Technologies, India

VLSI Verification Engineer from 12/2011 to 05/2013

5.DUART & I2C Verification

Project Description:

Wipro Technologies has one of the valuable client Freescale; Freescale Semiconductor is the leading manufacturer of microcontrollers, microprocessors and semiconductors. The objective of the project was to develop & validate test cases in system verilog for the blocks DUART and I2C, prepared verification plan and test case passing includes Regressions, Toggle coverage and Functional Coverage.

This project involves porting of test cases in to the newer version of SOC, Coding new test cases for the additional features of this SOC and Module level verification in an SOC.

Contribution:

As a team member responsible for Verification of DUART and I2C blocks

Created a test plan, which covers all the features according to the module specification.

Developed Test cases and Unit testing

Prepared Verification plan for DUART and I2C blocks also includes Regressions, Toggle coverage and functional coverage

Good understanding of existing testcases and mentioned the quality of code and coding style while creating new scenarios (testcases) for new features, extra checkers, missing scenarios, system verilog assertions.

Worked on Toggle coverage through missing scenarios and system verilog assertions.

Adding checkers to all the sequences to check the latest functionality.

Project Profile#6: Vision Krest Technologies, India

6.DDR3 SDRAM MICROCONTROLLER

Project Description:

Double Data Rate (DDR3) Synchronous Dynamic Random Access Memory (SDRAM) is quickly becoming the memory of choice mainly because of its ability to transfer the data on both rising and falling edge of the internal clock cycle (double pumping) which doubles the throughput when compared to conventional Single Data Rate (SDR) SDRAM. As processors gain speed, memory modules also need to support them so that the overall system performance maintained. Several manufacturers make DDR SDRAM, but they all follow the same standard interface.

Contribution:

Developed Verilog code for the design of DDR3 SDRAM controller

Implemented Read, Write, Burst write and fast read operations

Implemented Unit test cases

Education

M.Tech with Distinction (82.27%) and Topper in Digital Systems & Computer Electronics from Sreenidhi Institute of Science & Technology, JNTU-Hyderabad, India

B.Tech with Distinction (73%) in Instrumentation and Control Engineering from Vignan Institute of Technology & Science, JNTU-Hyderabad, India

Personal Details

Particular

Details

Name

SHWETHA BANDARI

Current Location

HILLSBORO,OREGON

Role

VLSI-Verification Engineer

Email ID

aczajn@r.postjobfree.com

Contact Number – Mobile

503-***-****

Work authorization

H4-EAD

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