Design Engineer

Madhuri Karumanchi

*******************@*****.***

Current Address:

***** ** ********** *** +1-971-***-****

Hillsboro, OR-97124

OBJECTIVE Seeking a Design Engineer position.

EDUCATION University of North Carolina at Charlotte Master of Science in Electrical Engineering,

Expected May 2017

SRM University, Chennai, TN, India

Bachelor of Technology in Electronics and Communication Engineering May 2015

TECHNICAL

SKILLS

Hardware Descriptive Languages: RTL Verilog, VHDL; Programming Languages: C, Perl EDA Tools: Cadence Virtuoso, Magic, Spectre Circuit Simulator, IRSIM, Synopsys HSPICE RELEVANT

COURSES

• VLSI System Design • Computer Architecture • Digital Systems • Fabrication of Nanomaterials

• Solid State Microelectronic Devices • Semiconductor Optoelectronic Devices • Advanced System Design using HDLs

ACADEMIC

PROJECTS

Design of 8-bit SRAM using TSMC 0.25-micron process, UNC Charlotte

• Implemented 8-bit SRAM circuit with column select and 3 to 8 decoder circuit.

• Implemented area optimized layout of the above design.

• Performed physical verification.

CMOS Layout and Extraction in TSMC 0.35-micron process, UNC Charlotte

• Designed a custom standard cell library.

• Ran DRC/LVS to complete the physical verification signoff for the layouts.

• Characterized the above gates by running HSPICE simulations. Design and Implementation of 16-bit RISC processor using VHDL, UNC Charlotte

• Implemented a four-stage pipelined 16-bit processor with 8-bit wide data memory, 8-bit wide address bus, sixteen 8-bit registers and a non-preemptive interrupt handler.

• Responsible for Integrating and testing the pipelined processor with interrupts. Design and Implementation of a four port Network Router using VHDL, UNC Charlotte

• Implemented a Network Router with 4 gateways with load balancing router control logic.

• Implemented Routing table using 64-bit wide RAM.

• Integrated and tested the router capability of load balancing under high packet traffic conditions and the average packet latency and throughput for 1000 packets is observed. Electron Beam Patterning by Optical Lithography, UNC Charlotte

• A grid of dimensions 5mm x 5mm is patterned on a silicon wafer with five different electron dosages using e-beam lithography and the reflectance is measured. Performance Analysis of GPUs, UNC Charlotte

• Profiled CUDA applications: 2D FFT Convolution algorithm, Monte-carlo Option Pricing algorithm, 3D Finite-difference Time-domain algorithm using NVIDIA Nsight on NVIDIA’s Maxwell GPU and Pascal GPU.

• Performed memory analysis and identified performance bottlenecks. Compiling and Profiling of benchmark files on X86 and X86_32, UNC Charlotte

• Compiled Dhrystone, Whetstone, Linpack benchmark files on two different micro-architectural platforms.

• Profiling of the benchmarks is made using gprof for various gcc compiler optimizations. Design of Carry Select Adder using Modified GDI Technique, SRM University

• Implemented a 16-bit carry select adder with Modified GDI technique in 180 nm technology using Tanner EDA tool. The implemented technique resulted in an area, power and delay efficient design.

RELATED

EXPERIENCE

Research Intern May 2014 - June 2014

Regional Center for Military Airworthiness, DRDO, AP, India Project – Design and Testing of Radio Altimeter

• Involved in the designing and testing of DSP based Radio Altimeter.

• Worked on the measurement accuracy of the altimeter for aircraft banking.

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