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Design Engineering

Location:
Portland, Oregon, United States
Salary:
80K
Posted:
February 12, 2018

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Resume:

GULROZ SINGH

www.linkedin.com/in/GulrozSingh ac4ftp@r.postjobfree.com 971-***-**** Portland, Oregon, USA Objective Seeking Full time / Internship position in Digital Design-Verification, Computer Architecture, Software Engineering. Education

M.S, Electrical and Computer Engineering, Portland State University (Fall’16 - Dec’18 expected) B.S, Electronics and Communication Engineering, GGSIP University (2012- 2016) (GPA – 3.7) Professional Experience

Scalable Systems Research Labs Inc., San Bruno, California, USA (July’17 – Sept’17) Intern – ASIC Design and Verification

o Worked with Design and Pre Silicon Functional Verification Team in the Memory Systems Group. o Design-Verification of Interpreter for an HMC based memory sub system IP having TCAM, SRAM, DRAM and Flash using SV. o Writing scripts, running tests and debugging results to find the source of error.

Graduate Teaching Assistant – Advance Computer Architecture (Sept’17 – Present), Engineering Computation (Jan’17 – July’17) o Responsible for homework assignments /projects on CPU simulators like Simplescalar and Champsim simulator involving implementing branch prediction, prefetching and cache replacement algorithms using SPEC CPU2006 benchmarks. o Designed lab exercises in MATLAB and Python, Conducted weekly lab sessions, Corrected lab assignments, exams, final project.

Silicon Mentor, Noida, India (June’16 – Aug’16)

Research Intern – SoC/ FPGA Design

o Worked on the project ‘Efficient Hardware Implementation of Image Watermarking Using DWT and AES Algorithm’ presented at an IEEE Conference Proceedings and included in IEEE Xplore. http://ieeexplore.ieee.org/xpls/icp.jsp?arnumber=7489093&tag=1 Courses

Computer Architecture Advance Computer Architecture-1 Intelligent Robotics Artificial Intelligence: Neural Networks Digital IC Design Application Specific Integrated Circuits (ASIC) Microprocessor System Design Pre Silicon Functional Verification Technical Skills

• RTL Design and Verification experience using Verilog, System Verilog and VHDL. Exposure to UVM

• Project experience and knowledge of memory subsystems, caches, virtual memory, various ISA’s and microarchitectures in general

• Exposure to basic Artificial Intelligence algorithm categories like supervised, unsupervised and reinforcement learning with projects in each one of the categories. Self Organizing Maps, T-SNE, Q learning are some of the specific algos that I have worked on.

• Basic Operating System concepts, OOPS concepts, Shell Scripting (basics)

• Scripting (Process Automation) experience using Python and coding experience in C, C++ and MATLAB

• Standards/ Bus Protocols: USB, UART and basic conceptual knowledge of other serial I/O industry standards.

• Tools: Xilinx Vivado, Questa/ ModelSim, Cadence Virtuoso, Synopsis DC Technical Projects

• PDP-11 Instruction Set Architecture (PSU - May’17) Language – C++, Implemented integer and floating point instructions, GUI for single stepping, displaying processor status (SP, PC, condition codes etc.) and setting breakpoints. Wrote test programs in MACRO 11 assembly language.

• YAGS Branch Prediction Scheme (PSU – June’17)

Language – C++, Evaluated performance by changing associativity and line size of Taken/ Not-Taken Caches. ChampSim Simulator was used to compare performance with other two-level branch prediction schemes like Bi-Mode, Filter, GShare and Agree Branch predictors.

• Simulation of an inclusive writeback 8-way L2 Cache in shared memory configuration (PSU - January’17) Language – System Verilog, Used MESI protocol for cache coherence, and True LRU replacement policy. Evaluated cache hit rate, conflict and coherence misses per 1000 accesses for a memory trace file by varying the associativity and line size.

• Design Verification of SDR SDRAM Controller using System Verilog (PSU – March’17) Created a stub for the target memory, Developed UVM environment with constrained random tests for various block and chip level features. Utilized covergroups, analyzed code functional coverage, improved test cases to meet desired coverage goals.

• Design of Reinforcement Learning Algorithm for a simulated humanoid robot (PSU – Dec’17) https://vimeo.com/246574745 Language – Python (libraries – OpenAI, Gym, Mujoco) Simulating Humanoid robot to standup, walk, run by exploring the environment and collecting rewards. Four optimized reward collecting schemes to collect performance and accuracy results.

• Application Specific Cryptographic Processor (PSU – December’ 16) Language – Python, Worked on designing, modeling, testing an ASCP for IDEA block cipher algorithm. Analyzed performance of processor comparing with existing implementations after literature survey. Massive Open Online Courses

• Machine learning - Stanford University on Coursera (96%) Communicating Strategically – PurdueX online (98%)



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