Atharva Pradeep Ponkshe

+1-503-***-**** Portland, Oregon

ac2fud@r.postjobfree.com https://www.linkedin.com/in/atharvaponkshe SUMMARY: Seeking full-time/internship opportunity in Silicon Hardware Design/Veri ication/Validation. EDUCATION

Masters in Electrical & Computer Engineering Sept 2015 – June 2017 Portland State University, Portland, Oregon (GPA: 3.49/4.0) Bachelors in Electronics and Telecommunication Engineering Aug 2011 – July 2015 V.E.S. Institute of Technology, University of Mumbai, India (GPA: 3.65/4.0) KEY SKILLS

● Programming: Verilog, SystemVerilog, C/C++

● Scripting: Tcl, Perl

● EDA Suite and Tools: Xilinx Vivado, Synopsys DC & ICC WORK EXPERIENCE

Project Volunteer Intern, HDL Express July 2017 - Present

● Designing Single Precision Floating Point Unit supporting RISC-V 32IM standard F-extension for the CPU implementing new micro-architecture.

● Using SystemVerilog for design, simulation and debug. GRADUATE PROJECTS

Lode Runner Arcade Game Implementation on Nexys4DDR FPGA board

● Developed the game in which single player tries to win against three opponents continuously following and trying to kill him; designed graphics for the game map, player icon and opponent icons in MS paint.

● Implemented underlying game logic using Picoblaze softcore processor and custom hardware modules.

● Utilized Xilinx Block RAM IPs to store pixel information of the map and icons and integrated them with custom video controller to render game graphics on VGA display; established keyboard interface for player control using off-the-shelf USB keyboard controller.

● Used Verilog for custom designs and Xilinx Vivado Design Suite for the entire game development on FPGA. Logical and Physical Synthesis of Asynchronous FIFO Buffer

● Studied RTL Design of the buffer and compiled it into a 45nm technology-dependent netlist using Synopsys DC and compiled this netlist into a layout using Synopsys ICC; explored different wire load models available in the technology library.

● Developed TCL automation scripts for inding net shapes between two pins given by a user, total length of the route between two pins and co-ordinates of the mid-point between two pins.

● Improved slack on a negative timing path by using ‘magnet placement’ command to pull standard cells towards a ixed macro. Studied hard, soft, partial and buffer only types of placement blockages; observed effects of ‘don’t touch’ command on optimization.

Modelling and Performance Simulation of Superscalar Micro-architectural schemes

● Implemented Per-Address Branch History-Global Pattern History(PAg) and gshare branch prediction, SRRIP, DRRIP and Evicted Address Filter (EAF) cache replacement policies and Stride prefetching technique in C++.

● Integrated these modules with the custom CPU performance simulator ‘ChampSim’.

● compared performance of every scheme with baseline CPU con iguration. Functional Verification of Two-way set associative cache controller

● Designed stimulus generator, driver and checker in SystemVerilog for the test environment using QuestaSim. GRADUATE COURSEWORK

SoC RTL Design with FPGA Digital IC Physical Design – I,II Pre-Silicon Functional Validation Post-Silicon Electrical Validation Microprocessor System Design Computer Architecture