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Design Engineer Electrical

Location:
Portland, Oregon, United States
Salary:
Open
Posted:
June 26, 2019

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Resume:

Thai Quoc Nguyen

**** *.*. ***** ****** 503-***-****

Portland, OR 97214 ac9o03@r.postjobfree.com

SENIOR HARDWARE ENGINEER

MSEE with hardware design experience and strong analog & digital circuit on board level, ASIC/FPGA design and signal integrity skills. Excellent team player, able to contribute immediately. U.S. Citizen.

Experience includes:

• High Speed Digital, Analog, Mixed and Power Electronic circuit board design

• High Speed Signal Analysis, Single-End and Differential Signal 3.125 Gbps SERDES & 2.5Gbps PCIe, LVDS, ECL & PECL, Eye Diagram Analysis, Design Testing, Debug and Release to Production

• High Speed Digital ASIC/Gate Array/FPGA/FPOA Design using Altera, Xilinx, Lattice, and MathStar

• Executing Test Plan on the High Speed Board and Signal Integrity: BER, Electrical/Optical Eye Diagram, Flight Time, Skew, Jitter & Signal Noise, to prevent problems of EMI, ESD and Reliability and achieve high speed execution

• Debug/Solve the Problems on ASIC/FPGA Chip and High Speed Digital & Analog Board Level Design

SKILLS

Design & Testing Tools:

• HSPICE & PSPICE, VeriLog HDL, OVN/UVM System Verilog and VHDL

• IBM PC XT/AT, Pentium, Pentium Pro Motherboard and I/O, PowerPC Architecture System Design, EGA, VGA, IDE & SCSI Hard Disk Controller Board

• Xilinx/Altera/Lattice and Synario/Synthesis Tools for ASIC Design using FPGA and HP ASIC Gate Array

• Agilent Far/J-BERT, HP Network Signal Analysis, Spectrum Analysis, TDR Impedance Analysis, High Speed Digital Oscillator Scope and Digital Analyzer

• Simulation and Layout using SUN/HP/PC system

Software Tools:

• Mentor Graphic Architecture, DS-Designer, PAD, Hyperlynx, Cadence Schematic, Allegro, Orcad and Altium

• Xilinx Vivado, ISE, Altera Quartus II, Lattice Diamond, Synopsys, Modelsim, Cadence NC, HSpice and Pspice

Languages:

• C- Languages (in Graphics, non-linear and numerical analysis programming) and Assembly Languages

Systems:

• Mainframe Computers: UNIX / VAX, IBM, GOULD & HONEYWELL Systems

EDUCATION

Master of Science in Electrical Engineering, Portland State University 1987

Bachelor of Science in Electrical Engineering, Portland State University 1985

PROFESSIONAL EXPERIENCE

HARRIS Corp. Palm Bay, FL 01/2019 – 06/2019

SENIOR HARDWARE ENGINEER

• Reviewed, corrected & redesigned all issues of analog, digital, power circuit and optical modulator circuit control, power distribution, power on sequencing and reset power sequencer circuits for high speed Xilinx Kintex UltraScale and Vertex UltraScale 7000 series FPGA on over 15 CCAs in Cypress System Product.

• Reviewed and corrected all layout PWB Board issues over 15 CCAs in Cypress System Product.

• Completed Mixed & Power Circuits Simulation in 15 CCAs with Pspice and LTspice. Used Mentor Graphics Hyperlynx pre & post-layout simulation for Single end, LVDS and PICe Gen2&3 high speed differential buses.

• Supported some engineers to complete the circuits design and the schematics of the CCA projects on time.

Bio-Rad Laboratories Inc. Hercules, CA 07/2018 – 12/2018

SENIOR R&D ENGINEER

• Completed LCD Display Module Control Circuit Design 3G system product in LTSpice simulation, Orcad Schematics, PAD Layout, Bring-up Test Bench, EMC/ESD Testing & Debug: High Speed LVDS Circuit Interface, Back-Light Circuits and Touch Screen USB Interface, and RGB LED Power Control circuit design.

• Completed design Buck & Boost Power DC-DC Converter circuits for 3G system product.

• Completed all high speed digital and analog harness connector & wire/flex cables design, testing & signal quality.

• Working on Thermal and Camera Board Testing Plan meet medical Bio-Rad requirements.

SpectraLux Avionics Corp. Redmond WA 11/2017 – 4/2018

SENIOR ELECTRICAL ENGINEER

• Completed debug and solved issues in Boeing 777 - PCU PWR & CNTL board: Digital interface STM32CubeMX microcontroller, Boeing CAN buses, I2C, and other component & assembly prototype.

• Completed design first prototype Boeing 777 – PCU Ahead board: digital & analog circuit design, high power design in PFC AC-DC & Isolation DC-DC Converter circuits, STM32CubeMX microcontroller, high power Class-D Amplifier circuit and Non-linear control Dome Light for Boeing 777 Project.

• Done all digital and analog circuits design and board layout met the test requirement of the DO-160 & DO254 and Boeing specifications.

• Completed LTSpice simulation in all critical analog & power circuits and DO-160 requirement testing: EMC, Lightning and signal integrity.

• All the circuits design has been done by Altium schematics & layout from A to Z: circuits design, schematics entry, schematics symbols, footprint and PCB layout in IPC-2222 & IPC-2223D design standard for Rigid Organic & Flexible/Rigid-Flexible Printed Boards.

• Built and bring up test bench for all the craft circuit board Class-D Amplifier, Analog Bandpass circuits and Linear Technology Evaluation Boards with modifying to meet product requirements.

ZincFive Inc, Tualatin, OR 9/2016 – 10/2017

SENIOR POWER ELECTRONICS ENGINEER

• Completed design first prototype high power controller of Nickel Zinc battery charge/discharge motherboard.

• Completed design mixed signal circuits and high-power circuits design in LTSpice simulation, schematic & layout using Altium designer: High power converter 120VAC to 48VDC, 48VDC to 120VAC, Voltage & Current analog circuits monitor for PFC (power factor control) and charge/discharge UPS (Uninterruptible Power Supply) controller, high-performance Atmel SMART SAM E70 Flash microcontroller & system on chip, 10/100 base-T Ethernet, CAN buses, eMMC, QSPI, LCD, SPI, I2C and analog & GPIO buses on board.

• Team work in design 12V Emulator for over 200 Amps: digital/analog control circuit design, LTSpice simulation, Schematics and Layout using Altium Designer.

DRS Technologies, Milwaukee, WI 12/2015 – 8/2016

SENIOR ELECTRICAL DESIGN ENGINEER

• Completed new technology and architecture design for power control system in US Navy Ship.

• Completed design mixed signal circuit design, schematic & layout new generic controller using Altium designer. Completed Hyperlynx pre & post-layout simulation, signal integrity of four channel serdes 6.25Gbps buses, DDR3, dual 1Gbps Ethernet, USB, CAN bus, eMMC, QSPI, SDIO, I2C and analog & gpio buses on board. Completed derating component list, reliability and validation plan to meet government requirement.

• Completed design high speed Xilinx Zynq7015 FPGA and VHDL codes of universal master I2C, over 100 GPIO interface using Xilinx Vivado 2015.4 & Modelsim and Pspice simulation for analog circuits on prototype board.

Advanced Energy Industries, Vancouver, WA 4/2015 – 11/2015

MIXED CIRCUIT DESIGN ENGINEER

• Completed debug & fix all the design issues of the Laser Current Source Interface Control Board.

• Completed design 8-small MXE source boards with different laser diode components.

• Completed the MXE High Speed Pyrometer Main Board Version 03 for high accurate thermal meter (ex, 0 – +2000 C-degree) in semiconductor equipment and other industrial equipment: modify, debug mixed circuits, schematics, PCB layout, debugs prototype board and release to production.

• Plan and build the Test Fixture for MXE Main Laser Control Board & System for manufacturing.

Lattice Semiconductor, San Jose, CA 10/2013 – 12/2014

STAFF PRODUCT VALIDATION ENGINEER

PCS (Physical Coding Subsystem) of high speed SerDes & PCS Block. Lattice FPGA Protocol Leader: PCIe, XAUI (IEEE 802.3ae-2002 for 10 Gb Ethernet), JESD204 (A&B) (ADC and DAC converter I/F), SMPTE SD-SDI, HD-SDI (292M), 3G-SDI (424M) and Gb Ethernet (IEEE 802.3-2005 1000BASE-CX, 1000BASE-SX and 1000BASE-LX), SGMII, CPRI (E.6.LV, E.12.LV, E.24.LV, E.30.LV, vers3.0).

MOHR Test and Measurement LLC, Richland, WA 09/2012 – 05/2013

SENIOR DESIGN ENGINEER

Worked on EFP-IL Interface board (for Navy dept. order to adding CT100), Analog/Digital and Power System design for CT100 product, Changed all Hardware Design from Eagle to Altium Schematic & Layout. Xilinx Spartan-3AN and VHDL codes for two FPGA projects: Digicom and Analog Board in CT100 Automated Metallic Time-Domain Reflectometers Product.

Dynamic Engineering. Santa Cruz, CA 02/2012 – 09/2012

SENIOR DESIGN ENGINEER

Worked on PCIe Verilog/VHDL Design in Lattice FPGA for aerospace System of Locked Martin System Products which are PCIe IP Core Ver. 1.0 & 2.0, DMA & FIFO of Hybrid/Fabric data packet transaction performance.

Xerox Corp., Wilsonville, OR 07/2011 – 01/2012

SENIOR ANALOG DESIGN ENGINEER

Worked on Pre-amp & Amplifier Interface Circuits Controller Board for two Pressure Sensors in Hydraulic & Solid-Ink System, two CIS (Contact Image Scanner) Interface, Title Sensor, Size Sensing and MSI (Multi-Sheet Inserter) Xilinx Spartan 3A FPGA for Step Motor, LVDS Bus and all Sensors Interface on Board. And Optical Interface Circuits in Xerox Solid Ink Printer System.

MOHR Test and Measurement LLC, Richland, WA 05/2011 – 09/2011

SENIOR DESIGN ENGINEER

Worked on Xilinx Spartan-3AN and VHDL codes for two FPGA projects: Digicom and Analog Board in CT100 Automated Metallic Time-Domain Reflectometers Product.

Stilwell Baker Inc., Hillsboro, OR 08/2010 – 12/2010

SENIOR ELECTRICAL ENGINEER

Worked on Master Controller Board for Deep Photonics Laser System: schematics & packaging by Altium.

Designed Microcontroller with Rabbit Microprocessor, Dynamic-C and other interface control circuits.

MathStar Inc., Hillsboro, OR 03/2008 – 06/2008

FPOA SYTEM DESIGN ENGINEER

Worked on Verilog codes Xilinx Vertex-5 8-lanes PCIe version 2, DDR2 memory controller, LVDS & GPIO buses.

Completed programmable FPOA Vegas Prime board: schematics & packaging by Cadence Allegro.

Lightfleet Inc., Camas, WA 09/2006 – 03/2008

SENIOR HARDWARE DESIGN ENGINEER

Designed optical power control circuit driver for VCSELs (Vertical Cavity Surface Emitting Laser) with bias, modulation & automatic power control current source, and high speed photo-detector circuit, TIA (Tran-Impedance Amplifier) and analog receive signal strength indicator.

Completed high speed optical test board: 3.125Gbps Laser Emitter and Photo-Detector circuits design to test new Lighfleet invent for the high speed light interconnection in the next high tech generation.

Completed EIO (Electrical Interface to Optical) board, 8 TX Laser Emitters and 32 Photo-Detectors, optical interconnection bandwidth is 3.125 Gbps BER 1E-12, and optical power diagnostic /alignment/ calibrate for 8 TX Laser drivers & 32 RX photo-detectors into the light-box interconnection.

Completed the high speed electrical loopback circuits design on EIO board run up to 4.25Gbps. All were designed by using Mental Graphics DS Designer.

Completed Design SERDES I/O, BERT (Bit Error Rate Tester) and 3.125 Gbit Data Serial Communication on the Lattice FPGA. Working on PCIe Data Transaction on Lattice FPGA.

Hewlett Packard Company, Vancouver, WA 05/005 – 09/2006

HARDWARE DESIGN ENGINEER

Worked on ASIC/FPGA Design Tester for HP Business Ink-Jet Printing System: Completed I2C, HP Mccii Buses, PWM&Tach, GPIO, PCI, PCIe, SATA, LVDS and SPI Master/Slave Controller.

Worked on Ink Assist, Motion, Drop Detect MICCI2 Bus and Other Power PC Buses.

Built System Tester board for business printer by using Cadence Orcad and Xilinx FPGA Vertex 5.

Polyvision Inc., Beaverton, OR 01/2005 – 05/2005

TEST DEVELOPMENT ENGINEER

Completed short-term contract to design and develop two test fixtures: the analog & digital circuit design in the ultrasound, and infrared transmitted & received systems that both test circuits are able to detect the different signal strength level of ultrasound and infrared energy.

RadiSys Corp., Hillsboro, OR 12/2004 – 01/2005

ANALOG DESIGN ENGINEER

Completed short-term contract for analog and digital board level design, checked, measurement and calculated all the detail circuitry on board.

Completed to build the part list of the Electronic Derating for Optimum Performance in order meet Agilent long term requirement. Suggested to change the circuit design to meet the reliability requirement of Electronic Derating for Optimum Performance.

DieBold, Inc.,North Canton, OH 2002 – 03/2004

SENIOR ELECTRONIC SYSTEMS ENGINEER

Completed Altera FPGA & VHDL Design for IDM Product (Intelligence Deposit Machine) for ATM: ARM7 & C515 micro-controller interface, stepper controller, sensor interface, clock controller, PWM controller, optical scan interface, magnetic scan interface, SPI controller, solenoid controller, ADC interface, and impact & inkjet printer controller.

Completed Magnetic Scanner Design for magnetic documents: analog circuits, analog board, mixed signal design, and calibrated & diagnostic circuit & firmware design.

Completed Altera FPGA & VHDL Design for Advanced IDM Product, E13-B&CMC-7 Hardware & Algorithm MICR scanner Design: analog, mixed circuits & digital circuits design, layout, test plan, algorithm/software recognition design, and double detected CMC-7 FPGA Controller.

Completed the Magnetic Imaging Scanner and USB Double Side Optical Scanner for Advanced IDM Product.

All products above were completed Design Phases: Theory Operation, Circuit design, Schematics, Altera FPGA, VHDL & Synthesis, Prototype Boards, Signal Analysis, Design Testing, Debug and Release to Production.

IMS (Integrated Measurement Systems), Inc., Beaverton, OR 2001 - 2001

SENIOR HARDWARE DEVELOPMENT ENGINEER

Completed research and design the new technology in development Rigel TestBoard (14” x 16”): high speed LVDS buses, 420MHz clock transmission and DDR (Double Data Rate) Synchronous Transaction from 840 Mb/s (1 LVDS bus) to 38.82 Gb/s (48 LVDS buses), high speed VHDM & VHDM-HSD Teradyne Connectors, Xilinx Virtex-II FPGA (XC2V1000 FF896) and Verilog-HDL codes. High speed Pipeline SRAM FPGA Double-Sided Mirror-Imaged for 18 & 36-Data bits, and ECL-PECL-LVDS Bus Translators, LVDS Clock Distribution Circuitry & Layout.

Executed Test Plan on the High Speed Board and Signal Integrity: Flight Time, Skew, Jitter & Signal Noise and BER (Bit Error Rate) of Single & Multiple LVDS Buses.

Wrote the Verilog-HDL for BER Testing in High Speed Single & Multiple LVDS Bus Transaction.

Hewlett Packard Company, Vancouver, WA 1998 - 2001

PRODUCT DEVELOPMENT ENGINEER

Worked R&D in Digital & Analog ASIC Chip, Main/Logic, Carriage PCA Design, tracked Logic PCA defect and helped solve those problems from concept to production for HP Ink-Jet Printer series 900.

Leaded design to complete to save 1.50 dollars per Broadway Main PCA unit (12 million units/year).

Took full responsibility for Digital ASIC chip rev. B, C, Solita & Helios, Analog Arabian chip and EE Product Quality (prevent problems of EMI, ESD & Reliability in Product Development Team.

Interfaced with HP-ICBD on Helios, Motorola on Arabian, designing, testing and problem solving related to defective Digital, Analog & Mixed ASIC and main PCA during design & validation phase.

Trained product engineers and set up Failure Analysis Station at HP-Singapore for Broadway product.

Worked in the new design technology team: VIP (Vancouver Image Pipeline), IR (Infrared), IEEE 1284 Bitronics, USB, IEEE 1394 Firewire, New LIO Buses (LVDS), Bluetooth System and Micro-controller.

INTEL Corporation, Hillsboro, OR 1995 - 1998

SENIOR DESIGN ENGINEER

Developed Heceta Mixed ASIC Chip, emulator board, FAT board and Altera FPGA(AHDL & VHDL).

Developed, executed test plan on Heceta Chip and Debugged and solved Heceta ASIC issues.

Completed Newport and Dublin (DB440FX) Motherboard in all Intel motherboard design phases.

Completed to design Ethernet (ICS1890), Wake On LAN (WOL) subsystems, low cost voltage regulator module, riser card, Super I/O PC87307, PIIX3/4, USB and Ethernet & WOL on board.

Completed to develop the first Intel LOM (Lan On Motherboad) Livermore Motherboard (First NET-PC Intel&IBM 440LX) with Pentium II Processor.

Developed and built 100 Base-TX and 10 Base-T IEEE 802.3 Test Fixture for Intel LOM.

Worked on High Speed Signal Integrity of Single End and Differential Signal Buses: GTL. PCI, ISA, USB, IEEE-1394, LAN (TTL, CMOS, Skew, Jitter & Noises for Motherboard products and designed in House BER Software Testing and Bit Error Rate Debug & Checking…).

Full responsibility in supporting LAN design for Intel Motherboard Division.

Worked on Hardware BIOS Hurlde Testing of Intel Alder Server System (Fab. 1 & 2) with three different operating systems: Windows NT Server & Workstation 3.51, NetWare 4.10 & 4.10 SMP, UnixWare 2.02. Debugged on Alder System & Main & CPU board and Orion Server ChipSet.

ATALLA TANDEM Company, San Jose, CA 1993 - 1994

TEST ENGINEER

Assisted in R&D Engineering Lab with responsibility for building the test procedure, writing C- and Assembly Languages to test, debug, and solve prototype hardware problems.

CORPORATE SYSTEMS CENTER, Sunnyvale, CA 1991 - 1993

Technical Service and Support Test

Completed projects CSC FASTCACHE 64 Harddisk Controller (SCSI & IDE) in hardware & software, wrote C and assembly language to test Maxoptics TAHITI 1, Maxtor hard drive (from 200MB to 1.7GB). Repaired used hard drive and customer return in clean room and debug PCB controllers.

COLORPREP Inc., Redwood City, CA 1989 - 1991

HARDWARE DESIGN ENGINEER

Worked on Imaging & Graphing Systems, developing Scanner, Composer and Output Film Systems.

Team work with Graphics & Color Adjust Algorithm in C-Languages for Optronics Scanner Projects.

Designed high resolution Video Controller card.

Worked on test, installation, quality assurance and maintenance Pre-Press Graphics Systems.

QUALOGY Inc., Milpitas, CA 1988 -1989

HARDWARE/SOFTWARE TEST ENGINEER

Wrote C and assembly language to test IBM PC XT/AT 286 &386 single motherboard, I/O, EGA & VGA graphics, hard disk & floppy controller, modem card and DEC system board and multibus board.

PORTLAND STATE UNIVERSITY 1985 - 1987

E.E. Dept. Teaching assistant and collaborated with professor Chung Yu Wu on High Speed VLSI Circuits Modeling and Simulation Program Design.

COURSE WORK and CONTINUING EDUCATION

• Advanced VLSI Circuits Design • VLSI Processing

• High Speed Signal Analysis & Design • CMOS VLSI Modeling

• Advanced Analog and Digital Integrated Circuits Design • System Electronics Design

• ASIC and Programmable Logic Design • Digital System Engineering

• Parallel and Distributed Architecture • Software Design

• Advanced Computer Architecture Systems • Memory Systems

• Microprocessor & Multiprocessor System Design • Switching Theory

• I/O Interfacing Design & Applications • Data Communication

• Advanced Digital Signal Processing • Optical Electronics

• Advanced Communication Theory • Instrumentation Systems

• Analog & Digital Modern Control Systems

• Operating System UNIX (C-Languages & C SHELL Programming)

• Computational Methods and Research Tools in Electrical Engineering (Non-Linear Optimization Programming)

SEMINARS

• LVDS I/O High Speed Circuit Design • Intel/PC Architecture • Signal Integrity

• High Speed On/Off-Chip Design • LAN Design & Testing • ESD

• On/Off-Chip Thermal Design • ASIC Project Planning • EMC

• On Chip Testing and Digital communication



Contact this candidate