Yogesh Dhada L

*** ** ***** *** *****:ac1waw@r.postjobfree.com

Hillsboro, OR 97124 Phone: 971-***-****

OBJECTIVE

Looking for a full-time position in Hardware/Software design and validation, available immediately. SKILLS

Language: C, C++, Java, Assembly, SQLite, Verilog, Python, Perl, Shell Scripting, OpenWRT, and Git. EDA tools: Code Composer Studio, Android Studio, Eclipse, Virtuoso, Vivado, Eclipse, Code Blocks. Expertise: RTL code, Debugging (JTAG & GDB), Linux Kernel, Firmware, Makefile, Validation, Emulation. Platform: FPGA, TI 32-bit microcontroller, Raspberry Pi, embedded Linux, Window, ARM and x86. WORK EXPERIENCE

Embedded Design and Test Engineer, Imperium-Electronics, Portland Jan’17 – Present

Responsible for generating software and hardware specification by analyzing features of the product.

Designing and Validating Firmware for SPI, UART, RF and Encryption modules on the microcontroller.

Responsible for leading technical team by motivating, advising, guiding and supporting. Graduate Teaching Assistant, System on Chip in Portland State University, OR Mar’16 – June’16

Was responsible for Verifying and grading projects using different test patterns on FPGA board. Embedded Test Engineer, Gnomic, India July’13 – Aug’14

Was responsible for optimizing and validating boot-time & configuration using BIOS & Kernel of Linux based microcontrollers, Sitara-AM335x board starter kit and Carambola 2 Software Development Kit.

Was responsible for testing Hardware application features using different test cases. ACADEMIC PROJECTS AND RESEARCH PAPER

Home Security Android Mobile app (Android Studio, Java, JSON, & SQLite)

Used AWS IoT, Raspberry Pi, and Z wave devices to monitor and control activities at smart home.

Developed Sign In, Request Access and Sign Out fragments to secure and navigate the App.

Created SQLite database to store user details and sensors data for offline or online mode. FPGA Audio Visualizer (Verilog, Assembly, ModelSim, Vivado Xilinx & Nexys 4 FPGA)

Displaying increasing amplitude bars in LCD TV based on input audio through MIC of Nexys4 FPGA.

Designed audio module for receiving audio input and filter through CRC IP and AXIS interface.

Implemented interface of PicoBlaze soft CPU and assembly code for changing color of amplitude bars. Cache Simulator (Code Blocks, C & python)

Designed L1 cache simulator using random replacement policy for 32-bit addressable processor.

Displayed number of memory accesses along with number of hits/miss, and number of cycle chart.

Implemented a random test case generator and compared with expected output patterns. Functional & Timing Simulator for MIPS (Visual Studio & C++)

Designed 5-stage MIPS 32-bit simulator which captures execution flow of instructions with registers.

Analyzed number of cycles required for execution in different modes of simulator (stalls, forwarding).

Tested simulator result by providing different inputs assembly code files which are given by professor. Scan cell based Carry Look-Ahead ALU (Verilog, Cadence RTL compiler & Encounter, Perl)

Designed ALU’s blocks adder, subtractor, multiplier and scan cell using standard cells from freepdk45.

Synthesis and place & route the design using 45nm technology standard library cells.

Applied test patterns using scan chain to verify the design for controllability and observability. Greatest Common Divisor-GCD (Synthesis, Static timing analysis, Perl, Encounter & Verilog)

Designed control path and data path logic with RTL model and FSM for calculation GCD.

Synthesized and place & route with Maximum clock frequency & I/O delays to optimize performance.

Created test environment with UVM, created test sequences and test patterns to verify block. Crosstalk – LAB (Electrical Validation Board, Oscilloscope)

Setup the Electrical Validation board for measuring crosstalk effects on the long routed nets of PCB.

Analyzed waveforms of victim nets on the oscilloscope for effects of crosstalk with different modes.

Studied effects of crosstalk and minimization techniques through lab and research papers. UART Verification - UVM (SystemVerilog, Mentor Questa, UVM)

Designed Baud Rate Generator, FIFO, Shift logic and Sub-system logic with RTL model and FSM.

Implemented test bench using Universal Verification Methodology for verifying functionality UART.

Constructed Sequencer, Driver, Monitor, Scoreboard, Checker and Virtual Interface for test bench. EDUCATION

M.S in Electrical and Computer Engineering, Portland State University, OR GPA - 3.6 Dec’16 B.Tech in Electrical and Communication Engineering, LPU, India GPA - 3.6 June’12 COURSEWORK

Modeling and Synthesis: ASIC Digital IC Design-I Advance Computer Architecture Post-silicon Electrical Validation Digital IC Design-II Embedded System Programming Formal Verification of HW/SW System on Chip (SOC) Computer Architecture

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