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CPU Performance/Design Verification Professional Experience

Portland, Oregon, United States
November 27, 2017

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Obtaining a full-time position in Computer Architecture, RTL Design, Verification and Validation. PROFESSIONAL EXPERIENCE

CPU Performance Architecture Intern, NVIDIA: Beaverton, OR (Oct’16-Jan’17)

Configured the performance model for different test cases targeting design components like cache hierarchy.

Planned and wrote microbenchmarks targeting RTL units of ARM compliant CPU core in assembly language.

Correlated cycle count, after microarchitecture review, with simulator for identifying performance bottlenecks. CPU design verification Intern, HDL Express, Canby, OR (Jul’17-Current)

Verification of out of order processor blocks - decode, microcode & ALU. Used RISC-V assembly for debugging.

Developed checker,scoreboard in SystemVerilog & automated the test environment using a make script. EDUCATION

MS, Electrical & Computer Engineering, GPA 3.66 BE, Electronics & Telecommunication Engineering, GPA 3.63 Portland State University, (Sep’15-Jun’17) University of Pune, (Aug’11-Jun’15) TECHINCAL SKILLS

Programming : SystemVerilog, SystemVerilog Assetions, Verilog, C,C++, Python, Assembly, MATLAB, Perl Tools : Synopsys DC, Design Vision, Questasim, Cadence Virtuoso, Vivado Other Skills : Linux, Git, Perforce


Constraint Random Functional Verification of L1 cache with MESI protocol (SystemVerilog) (Feb’16-Mar’16)

Designed stimulus generator and driver to create pre-generated, random-leaning stimuli.

Employed Transaction-based checking & monitored coverage for directed or constrained-random test cases. System on chip “Hunter’s paradise” game (Verilog/Artix7 FPGA/PicoBlaze/Android) (Apr’16-Jun’16)

Implemented randomizing RTL logic & VGA controller in synthesizable verilog for controlling image icons.

Wrote firmware in Picoblaze assembly and used Xilinx’s block RAM IP for storing bitmaps containing image data. Multilevel memory controller (Verilog) (Nov’15-Dec’15)

Designed hierarchical memory controller, controlling and handling requests from three devices.

Tested and optimized the design for the tradeoffs between memory cost, communication cost and latency. Application Specific Cryptographic Processor (Assembly/Python) (Jan’16-Mar’16)

Designed instruction set architecture and microarchitecture based on MIPS architecture.

Implemented 5-stage pipelined processor’s simulator achieving high throughput and low latency. Simulation and analysis of Multiprocessor Cache Coherence System (C++/Python) (Feb’17-Mar’17)

Simulated and compared performance of L1 cache coherence protocols MESI and MI.

Generated a trace containing memory requests for different processors sharing bus. Design and Logic Synthesis of Synchronous FIFO (SystemVerilog/TCL/Synopsys DC/Perl) (Feb ’17-Mar ’17)

Synthesized and generated netlist and run post synthesis simulation on the generated netlist.

Applied timing constraints and analyzed various critical paths in the circuit. Parallel computing with POSIX threads(C/MPI/pthreads) (Jan ’17-Feb’17)

Developed multithreaded program using pthreads for pi calculation and heat propagation. Multithreaded application for DC motor control (Artix7 FPGA/Microblaze/C/Xilkernel/RTOS) (Feb’17-Mar ’17)

Configured board support package & kernel parameters for PID control using message queues & semaphores.

Wrote device drivers to control from AXI(AMBA) peripheral custom IC via external circuit in soft core processor. Gesture controlled Bot(FPGAarduino/Artix7 FPGA/Android/OpenCV/Python) (Feb’16-Jun’16)

Captured real time video for detecting hand gestures & communicated via serial communication to FPGA board.

Used WIFI module ESP8266 and FPGAarduino for connecting and taking commands from android device & PC. ACADEMIC COURSEWORK

Microprocessor System Design Superscalar Processors (Adv Comp Arch 1) Parallel Processors (Adv Comp Arch 2) Presilicon Functional Validation SoC/Embedded Systems Design with FPGA Data Structures and Algorithms ACHIEVEMENT

First runner up in college level Texas Instruments Innovation Challenge of Circuit Designing.

+1 503-***-****

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