| Resume alert | Resumes 141 - 150 of 796 |
Design Project
Koramangala, Karnataka, India
... Skill Set EDA Tools : Cadence Virtuoso, Innovus, NCLaunch, encounter, Tempus and Vivado, Cadence Orcad, ICC2 Hardware Description Languages : Verilog. Software Skills : C-Programming. Platforms : Linux, Windows. Hardware Systems : NXP ARM Cortex M3 ... - 2019 Aug 07
... Skill Set EDA Tools : Cadence Virtuoso, Innovus, NCLaunch, encounter, Tempus and Vivado, Cadence Orcad, ICC2 Hardware Description Languages : Verilog. Software Skills : C-Programming. Platforms : Linux, Windows. Hardware Systems : NXP ARM Cortex M3 ... - 2019 Aug 07
Engineering Project
Kumaraswamy Layout, Karnataka, India
... System – 8051,8086-Keil Software (Intermediate) VHDL & Verilog Programming in Xilinx (Intermediate) LabVIEW (Intermediate) MATLAB (Beginner) Python (Beginner) Winners Telecombat 2019 2nd National level project Contest organized by IEEE with Dept. ... - 2019 Jul 31
... System – 8051,8086-Keil Software (Intermediate) VHDL & Verilog Programming in Xilinx (Intermediate) LabVIEW (Intermediate) MATLAB (Beginner) Python (Beginner) Winners Telecombat 2019 2nd National level project Contest organized by IEEE with Dept. ... - 2019 Jul 31
Information Technology Data
Bangalore, Karnataka, India
... SKILLS Python MATLAB C programming Modelsim Verilog Multisim Code composer studio (CSS) MS-Office Tensor Flow OPERATING SYSTEM windows, Linux- Ubuntu, Fedora, Zorin POSITIONS OF RESPONSIBILITY Organized and hosted for Cultural Events As a part of ... - 2019 Jul 28
... SKILLS Python MATLAB C programming Modelsim Verilog Multisim Code composer studio (CSS) MS-Office Tensor Flow OPERATING SYSTEM windows, Linux- Ubuntu, Fedora, Zorin POSITIONS OF RESPONSIBILITY Organized and hosted for Cultural Events As a part of ... - 2019 Jul 28
Test Cases Engineering
Bangalore, Karnataka, India
... Projects Thesis Hardware Trojan detection using Deep Learning technique Tools Used Synopsys Tetra Max Languages Used Verilog, Python Based on controllability and transition probability analysis, trojan nodes are isolated using deep learning ... - 2019 Jul 28
... Projects Thesis Hardware Trojan detection using Deep Learning technique Tools Used Synopsys Tetra Max Languages Used Verilog, Python Based on controllability and transition probability analysis, trojan nodes are isolated using deep learning ... - 2019 Jul 28
Engineer Project
Vasant Nagar, Karnataka, India
... Technical Skills Programming Languages C, Verilog HDL and System Verilog Methodologies Universal Verification Methodology Tools EDA play tools, Questa sim-64 10.6c Protocol Knowledge AMBA-AHB Lite, APB Digital Electronics and Basics of MPMC and VLSI ... - 2019 Jul 25
... Technical Skills Programming Languages C, Verilog HDL and System Verilog Methodologies Universal Verification Methodology Tools EDA play tools, Questa sim-64 10.6c Protocol Knowledge AMBA-AHB Lite, APB Digital Electronics and Basics of MPMC and VLSI ... - 2019 Jul 25
Engineer Test Cases
Vasant Nagar, Karnataka, India
... Good Programming Skills in Verilog, System Verilog, UVM. Decent working knowledge on standard protocols like AXI, APB, UART. Strong understanding of Assertion Based Verification & Functional Coverage. Hands on experience in writing test cases, ... - 2019 Jul 21
... Good Programming Skills in Verilog, System Verilog, UVM. Decent working knowledge on standard protocols like AXI, APB, UART. Strong understanding of Assertion Based Verification & Functional Coverage. Hands on experience in writing test cases, ... - 2019 Jul 21
Design Engineering
Vasant Nagar, Karnataka, India
... Pincode-560083 Mobile: +91-954******* LinkedIn ID: https://www.linkedin.com/in/manibhargav-ogirala-23a518172/ Summary of Qualifications Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models using Verilog HDL. ... - 2019 Jul 12
... Pincode-560083 Mobile: +91-954******* LinkedIn ID: https://www.linkedin.com/in/manibhargav-ogirala-23a518172/ Summary of Qualifications Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models using Verilog HDL. ... - 2019 Jul 12
Verilog, System Verilog, UVM, SOC Verification, ASIC Verification
Vasant Nagar, Karnataka, India
... The following are the best skills which I believe are applicable to the position I have applied for HDL : Verilog HVL : System Verilog Protocols : AMBA, AHB, APB, SPI, AHB-APB Simulators : Riviera Pro, Questasim, Modelsim Verification Methodologies ... - 2019 Jul 08
... The following are the best skills which I believe are applicable to the position I have applied for HDL : Verilog HVL : System Verilog Protocols : AMBA, AHB, APB, SPI, AHB-APB Simulators : Riviera Pro, Questasim, Modelsim Verification Methodologies ... - 2019 Jul 08
Engineering Software
Vasant Nagar, Karnataka, India
... University 2019 7.69(CGPA) *TECHNICAL SKILLS * COMPUTER LANGUAGES C, C++(beginner), Python HARDWARE LANGAUGES HDL (VHDL, Verilog HDL), Logic Designs, PLC COMPUTER LANGUAGES Microcontroller 8051, Microprocessor * PROJECTS DETAILS * SONAL PROFILE * * ... - 2019 Jul 01
... University 2019 7.69(CGPA) *TECHNICAL SKILLS * COMPUTER LANGUAGES C, C++(beginner), Python HARDWARE LANGAUGES HDL (VHDL, Verilog HDL), Logic Designs, PLC COMPUTER LANGUAGES Microcontroller 8051, Microprocessor * PROJECTS DETAILS * SONAL PROFILE * * ... - 2019 Jul 01
Engineer Design
Karnataka, India
... VLSI Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models using Verilog HDL. Good experience in writing Test benches using SystemVerilog and UVM Very good knowledge in verification methodologies TOOLS ... - 2019 Jun 17
... VLSI Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models using Verilog HDL. Good experience in writing Test benches using SystemVerilog and UVM Very good knowledge in verification methodologies TOOLS ... - 2019 Jun 17