Engineer Project

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Name: BJ SIVAPRASAD Email: ac9wid@r.postjobfree.com

Phone: +91-996*******

Role Design and Verification Engineer

OBJECTIVE

Young, Enthusiastic Engineer looking for an opportunity in electronics engineering and to be associated with a team that works dynamically in Electronics and VLSI technology. Training Experience

Engineering trainee at IFCS Technologies (from Oct 2018 to present).

9 months internship experience in Zakti group in VLSI (from Jan 2018 to Sep 2018). Technical Skills

Programming Languages C, Verilog HDL and System Verilog Methodologies Universal Verification Methodology

Tools EDA play tools, Questa sim-64 10.6c

Protocol Knowledge AMBA-AHB Lite, APB

Digital Electronics and Basics of MPMC and VLSI.

Hands on experience on Vim (editor), Linux and GIT version controller. Education

Post Graduated (2017) (Electronics and Communication) from S.S.B.N Degree & PG College Autonomous, Anantapur.

Project 1

Title AHB lite Master verification using UVM

Description

This project involves the functional verification of AHB master RTL using UVM based test bench. The UVM test bench contains two agents and scoreboard logic. One agent - UI agent is used to generate transaction towards AHB master through user interface. The other agent - AHB slave agents interacts with AHB master through AHB interface. AHB protocols were checked by AHB slave agent. Data sent from UI and data received at AHB slave agent were compared in the scoreboard to check the data integrity. Different scenarios like Single, INCR and WRAP burst transactions for write and read operations were verified using the above environment. Methodology UVM

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Responsibilities

Understood the AHB-Lite protocol specification.

Prepared verification plan based on design specification.

Developed slave logics to drive by master.

Verification by running test cases and collected responses from the DUT and compared results with the expected values.

Project 2

Title APB -2/3/4 verification IP using UVM

Description

APB (Advanced Peripheral Bus) is one of the components of the AMBA bus architecture. APB is low band width and low performance bus used to connect the peripherals like UART, keypad, Timer and other peripheral devices to the bus architecture. In this Project we developed the Environment architecture and DV plan and also developed multiple test cases, modelled scoreboard, and achieved functional coverage.

Methodology UVM

Responsibilities

Understanding the AMBA APB-2/3/4 protocol specification.

Configurable TB integration.

Driver component development – configured as Master.

Proactive Master driver.

Support of reset aware mechanism in configurable master agent.

Verified slave/master DUT with configurable test bench.

Sequence and test case development.

Regression and Debugging.

Project 3

Title Dual-Port Random access memory

Description

This one will support for both write and read operations by using the two ports one from write port and read port with two difference clock domains as well as the same clock domain.it will support for back write and read and continuous write and read operations.

Language Verilog and System Verilog

Responsibilities

Read and understood specification.

Developed the Verification plan and test plan.

Developed the test cases for verifying the design.

Integrated design and test UVC in test bench.

Verified with lookback modes.

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Project 4

Title Asynchronous FIFO

Description

This project focused on write and read performing in different clock domains by taking care of the FIFO full and empty conditions. And using the data synchronizer for the purpose of the sync the data for respective clock domains and gray to binary vice conversion for the write and read pointers.

Language Verilog and System Verilog

Responsibilities

Developed architecture for the design.

Worked on RTL write control blocks design and implementation.

Developed Verilog test bench and integrated with design Declaration

I hereby declared the above information is true and genuine to the best of my knowledge and belief. If am selected in your esteemed organization I shall prove my best and ability to the entire satisfaction of my superiors.

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