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Resumes 1 - 10 of 318 |
Sunnyvale, CA
... Research Assistant, VLSI Research Lab, State University of New York, Aug., 2000~Sep., 2007 ● Memory/Register File Design, Modeling and Testing (PhD Dissertation) ● Memory Circuit Design and CAD Tool Development: Power-aware memory system design for ...
- Apr 17
Cupertino, CA
... VLSI and UVM experience. 8/98-1/00: Seagate Technology, Scotts Valley, CA Sr. Advisory Development Engineer, developed SPICE models of CMOS SCSI transceivers using HSPICE. Performed bench testing of transceivers in lab. Other projects included PCB ...
- Mar 23
Sunnyvale, CA
... Citizen CAREER SUMMARY Over twenty years of experiences in low power, high performance, area efficient AI instruction set architectures, VLSI ASIC, ML, automotive, IoT physical designs, from RTL to GDSII semiconductor tape-out, electronic design ...
- Mar 10
Santa Clara, CA, 95050
... Training -Basics of Analog,Digital and VLSI concepts. Karmic Design Pvt Ltd, India (Aug 2011 – Dec 2012)
- Feb 21
Los Gatos, CA
... operations, logistics, customer support, KPI management, research and development, manufacturing/test (National Semiconductor, VLSI, AMKOR, TSMC), NPI, budgeting, cost management, quality programs, program management tools, stakeholder engagement, ...
- Jan 26
San Jose, CA, 95126
... India Jul 2018 – Jul 2022 Bachelor Of Engineering – Electronics & Communication Courses – Network Theory, Digital Design, Analog Electronics, Electronics Devices, Computer Organization, Power Electronics, CMOS VLSI design, Control Systems. ...
- Jan 10
San Jose, CA
... I was hired to recruit for the VLSI, SW and Product Engineering teams. I soon took over the software re- cruiting responsibilities as well. In 2001 I started managing Transmeta’s recruiting efforts. I was in charge of a team of 3. We recruited all ...
- Jan 10
Fremont, CA
... Certifications: ● Tableau Desktop Specialist ● Microsoft Azure Data Fundamentals (DP-900) ● Python (Beginner -Level) Certification with Numpy,Pandas, SciPy and MatplotLib Education: ● Masters of Technology in VLSI Design and Embedded Systems from, ...
- 2023 Nov 22
Dublin, CA
... Technician Aug 2004- July 2005 EDUCATION ● Masters in Engg(VLSI & EMBEDDED SYSTEMS)-(First Class) Pune University. ● Bachelors in Electronics Engg-(First Class) from Pune University. ● Diploma In Electronics-(First Class) from Board of Technical ...
- 2023 Aug 08
San Jose, CA
... PUBLICATION “APTMC: An Interface Program for use with ANSYS for Thermal and Thermally Induced Stress Modeling and Simulation of VLSI Packaging”1987 ANSYS Conference Proceeding, 11.55-11.62.
- 2023 May 30