Brunda Kodigenahalli Ravi Kumar

Role: AMS Verification Engineer

Email: ad3tc9@r.postjobfree.com

Mob: +1-503-***-****

Visa Status: H4 VISA with EAD (Valid till April-2026) EXPERIENCE SUMMARY

* ***** ** experience with expertise in Analog Mixed Signal design verification in Karmic Design Pvt Ltd, India.(Design Service Company)

Worked with clients- Texas Instruments-India,TI-China,TI-Dallas, and Infineon technologies, India.

Experienced in Verification of Power management IC's, Battery management IC and PMU IPs for SOC.

Experienced in activities: Specification study, Verification plan preparation, Test-case and TestBench Development, Discussions across team (analog, digital and systems), regressions and review sign-off.

Behavioral modeling of Power management analog blocks primarily in Verilog-AMS, SystemVerilog-RNM and VHDL-RNM.

Top-level simulations, Analog-Digital Co-simulations (AMS) to verify analog modules from top-level.

Experience in SystemVerilog-UVM Test-bench environment development and SystemVerilog Assertions and Coverage.

Well-versed with tools and simulators like Cadence-AMS Xcelium, Cadence ADE-L, Virtuoso Schematic Editor.

Knowledge of scripting languages Perl and TCL, version control management tools and different OS.

Knowledge of communication protocols like I2C, SPI.

Training and mentoring junior engineers on System Verilog, Verilog AMS basics and Verification flow. QUALIFICATION

Bachelor of Engineering in Instrumentation Tech: 2007-2011, B.V.B CET, India. PROJECTS

Power management unit of SOC Client: Infineon technologies, India (July 2020 – March 2021)

• Setup and run functional tests to verify the functionality and interactions at IP level.

• AMS Co-simulation with analog blocks configured in different modes and coverage tests.

• Experienced in verifying legacy testcases with modifications as a part of Functional verification. Verification of Low Power PMU Client: Texas Instruments, India (September 2019- February 2020)

Worked extensively on AMS Setup for the PMU-IP for AMS Verification.

Implemented checkers for auto checking in SystemVerilog and Verilog-AMS.

Verify the power domain connectivity wrt design hierarchy and UPF. Verification of mixed signal modules of Audio Amplifier Client: Texas Instruments,China (Oct 2018-August 2019)

Setup milestones, evaluate and modify existing UVM environment and Top-level TB for the device.

Created a DV plan and involved in test-case development.

Top Level Validation which included checking the functional behavior of blocks like PLL, LDO, Reference genarators from top level and their connectivity with digital.

AMS simulations for electrical parametric and functional verification.

Implemented checkers for auto checking in SystemVerilog and Verilog-AMS Verification of Isolated DC-DC converter Client: Texas Instruments,Dallas (Sep 2017-Aug 2018)

Setup the SV environment and Top-level TB for the device.

Setup milestones and DV plan and testcase development.

Behavioral modeling of analog blocks LDO, Reference, Oscillator and verifying the block’s functionality.

Top Level Validation which included checking the functional behavior of blocks from top level and their connectivity with digital.

AMS simulations for electrical specification verification.

Post layout extracted AMS simulation and GLS simulations to check for timing violations. Verification of mixed signal modules in PMIC. Client: Texas Instruments, Dallas (Aug 2016 -Feb 2017)

Behavioral modeling of blocks like LDO, Buck converter in VHDL, and verifying the block’s functionality.

DV plan, testcase development and testplan reviews.

Top Level Validation to check functional behavior of blocks and their connectivity with digital.

AMS simulations for the modules for electrical specification verification.

Run top-level GLS simulations and check for violations. UVM and System Verilog training project by CVC Karmic Design Pvt Ltd (Jan 2016- June 2016) Behavioral modeling of the Analog design modules in Verilog-AMS.

Building up the layered testbench Environment structure in system Verilog.

Run code coverage and analyze, verifying the functionality of the DUT using SV test bench

Understanding the structure of UVM hierarchy and building up component classes by extending the UVM base classes.

Constructing different sequences of objects to drive the DUT and run Functional coverage, analyze. Verification of Wired linear charger Client: Texas Instruments, Dallas (Jan 2015- December 2015)

Verification of charger blocks functionality –charge profile, current limits.

Top Level Validation included checking digital functionality, functional behavior of blocks from top level and their connectivity with digital.

AMS simulations for the charge profile verification.

Environment development by adding automated checkers in system Verilog. Block level and top-level verification of PMIC Client: Texas Instruments, Dallas (Feb 2013-Sept 2014)

Modeling of analog blocks like LDO, Buck-Boost converters, OTP, Testmux and other analog modules in VHDL and Verilog-AMS (Electrical and Wreal).

Development of self-checking System Verilog and TCL based test cases for regression, including some SV assertions.

Functional verification of the RTL from top level full chip simulations with analog blocks modeled in Verilog-AMS or VHDL. Gate level simulations to identify timing related issues.

Digital verification targeted towards full Functional and Code coverage by setting up directed as well as constrained random stimulus.

AMS simulations for electrical parameters validation. Training -Basics of Analog,Digital and VLSI concepts. Karmic Design Pvt Ltd, India (Aug 2011 – Dec 2012)

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