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Wanling Wen

408-***-****

ad38x7@r.postjobfree.com

U.S. Citizen

CAREER SUMMARY

Over twenty years of experiences in low power, high performance, area efficient AI instruction set architectures, VLSI ASIC, ML, automotive, IoT physical designs, from RTL to GDSII semiconductor tape-out, electronic design automation (EDA), field engineering, and firmware development

Outstanding hands-on experiences in hardware-software, front-end-back-end architectural co-design cutting edge AI processors

Proven track record of AI processor silicon tape-out and streamlined logic synthesis, place and route, Fusion RTL, physical-aware multi-hierarchy, low-power ASIC synthesis, floor-planning, scan-DFT, clock gating, STA, verification and ir-drop and power analysis for FinFet 7nm

Extensive experiences and in-depth understanding with place and route, IR-drop, power and timing closure and signoff, extraction for high frequency designs with custom hand placement of logic for better PPA and meeting time- to-results

Excellent design, implementation and configuration for VLSI ASIC designs, P&R strategies of all stages, trouble shooting and root cause analysis for floor-plan, power grid, P&R, CTS, signal and power integrity, static timing analysis, ir-drop and power analysis, physical verification, DFM

Field engineering, working with customers in their offices with professional decorum, selling innovative technologies and solutions, supporting customers' needs, resolving issues for customers, providing technical training for customers, winning more and more contracts/sales for my employers and achieving more and more customers' successes

Initiation of breakthroughs for EDA, IC designs and AV contents collaborations for business wins and successes of all parties, open-up of opportunities, working with customers and cross-functional teams for creation and execution of winning strategies

Proficiency with EDA tools and flows, such as IC Compiler, Innovus, Star-RC/QRC, Primetime/Tempus, PTPX, Design Compiler/Genus, Redhawk/Voltus, IC Validater, Pegasus, Library Compiler, Calibre, Custom Compiler and VCS/Xcelium Simulation, Conformal...

Tcl/TK, C/C++, Python, Unix shells, Chisel, Perl, Sed, Awk, UPF, Java

Developed new algorithms to improve by 20x the runtime of EDA flows using C/C++

Perform floor-planning, power grid architecture, placement, CTS, routing, signal integrity, physical verification for designs that include embedded memories, SRAM, analog PLL, I/Os and logic libraries in 7nm/10nm/14nm/22nm

Experiences with logic synthesis, power analysis, RC extraction, cell-placement, wire-routing, static timing analysis and low power algorithms in designs and tape-outs

Excellent communication and interpersonal skills EDUCATION

BA, Computer Science, University of California at Berkeley, Berkeley, CA, 2000 PROFESSIONAL EXPERIENCE

March 2021 – Present Lucid Circuit, Santa Monica, CA (Remote) Senior AI Chips Physical Design Engineer Lead

Design, develop and tape-out edge AI chips for aerospace, automotives, and IoT, from RTL to GDS o Design, implement and tape-out FinFet AI chips with best PPA o Develop power efficient design flow methodologies that include logical synthesis, floor-plan, placement, clock tree synthesis, routing, optimization, rc-extraction, static timing analysis, DRC, LVS, silicon-DFM, power synthesis and analysis, EMIR analysis, formal verification, simulation of the whole chip, including top level and block level, using Cadence tools

o Participate in hardware-software, front-end-back-end architectural co-design and enhancement o Write Python code to auto distribute hard-macros for best results beyond EDA tools' capability o Participate RTL coding edge-cutting AI processors in Chisel and integration of RTL design to streamlined design flows

o Integrate analog components to mixed signal designs July 2019 – March 2021 Diversified, Santa Clara, CA Page 2 of 5

Field System Engineer Lead & Embedded Programmer

Worked on field system engineering and commissioning on customers sites leading team members; worked with sale executives to campaign for more sales opportunities and business successes o Performed system engineering and commissioning with firmware, software on DSP, audio/video processors, controls, connections, amplifiers, transmitters, receivers, UI and I/O on customer sites o Wrote spec's and design components of configuration and conditions of networks, protocols and AV systems. Integrate speakers, microphones, acoustic solutions, projectors, displays and cameras using Simpl Windows, Extron Control Professional, Lua and Q-Sys Designer o Designed and developed firmware for AV, power, networks and digital conferencing systems using Lua, Python, Simpl and C#

o Debugged system failures on customer sites. Communicate with different levels and cross-functional clients/customers and members to improve and deliver products. o Applied advanced logic controls, signal processing on user inputs and system behaviors to build and validate robust complex stereo audio, 4K/8K video, intelligible telephony, remote 3D conference technologies for University of California, Google, JPMorgan Chase, Bank of America, DropBox, HPE, Aruba, Snap, Northeastern University, Chevron, Facebook...

Used statistics to analyze customers request data, such as number of conference rooms to be engineered, different types and sizes of rooms, different audio, video and network requirements and special needs o Applied customers' input data and analysis results to guide conference rooms sales, designs and engineering, projects planning, equipment purchases, labors request, distribution and scheduling o Collaborated among team members to deliver projects and archive successes of the company and customers Nov 2012 – May 2019 Synopsys Inc., Mountain View, CA Staff ASIC Physical Design Engineer

Spec’d, designed and taped out million-gate, multi-hierarchy ASIC with ultra-high performance and low power semiconductor designs with achievement of best PPA and EM/IR goals; helped achieve millions-dollar businesses of EDA, embedded memory compilers and standard cell libraries, CMOS o Performed place and route fusion, DC RTL synthesis, scan, ICCII/I, floor-planning, power grid architecting, placement, CTS, routing, optimization, parasitic extraction, STA, IR/EM/power analysis for designs, including embedded memories, analog PLL, I/Os and logic libraries in 7nm/10nm/14nm/22nm FinFET technologies of world's biggest semiconductor foundries, Global Foundry, Intel, TSMC, Samsung, UMC, and SMIC using ICC2/ICC/PT/RedHawk/DC

o Designed, implemented and trouble-shot steam-lined infrastructures, scripts, flows and methodologies for all stages of physical design and verifications, including licenses, foundries collaterals and requirements management

o Verified IPs for applications of artificial intelligence, 5G broadband networks, automotives, IoT, power motors, medical and others

o Created efficient design planning, including power grid and power mesh designs, with tape-out closures look-ahead using ICC2

o Applied logic synthesis, power analysis, RC extraction, cell-placement, wire-routing, static timing analysis, timing closure and low power algorithms in designs and tape-outs using ICC2/Prime-Time/Star-RC o Analyzed design performance using both hierarchical, flat approaches, reflecting design variation concerns with Prime-Time

o Evaluated dynamic, static IR drop, power analysis and ESD reliability using RedHawk and Totem o ECO fix timing and power

o Used Custom Compiler for routing enhancement

o Performed simulation analysis using VCS

o Physical verification, LVS, DRC, using ICV/Hercules/Calibre, for tape-out sign-off o Led and collaborated with team members to develop design specifications and methodologies to complete designs from RTL to GDS

o Ensured designs met performance, power and reliability signoff requirements and LVS/DRC clean

Worked on projects for reducing the area size and power consumption of embedded memories, including high-speed, high-density SRAMs, ROMs, DRAM, register files, eMRam, TCAM, closely coupled to processors memory compilers, standard cells, power optimization kits and optional overdrive/low voltage PVTs that enable designs to achieve maximum performance with the lowest possible power consumption for their specific applications o Communicated with customers to discuss project planning, issues, resolutions, connecting team members and customers

Designed and developed Tcl, Perl, C/C++, Python programs and automation methodologies to improve design turn- around times

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Led team members, mentored junior engineers and interns to improve throughputs of the team successfully Oct 2011 – Nov 2012 AMD, Sunnyvale, CA

CAD Design Engineer, Member of Technical Staff

Designed and developed integration software using breadth first search and other algorithms to enable physical designers to perform buffer insertion and close timing within Cadence’s Encounter using C/C++, Tcl for APU, CPU and GPU designs

Enhanced full chip floor-planning flows to support black-box floor-planning, partitioning, placement and ILM generation using Synopsys IC Compiler and feed-through insertion using Cadence’s Encounter

Enhanced the full chip netlist flow by integrating a new Verilog parser and writer o Used the APIs from the parser to remove the repeaters modules for RTL designers to reuse designs o The netlist with repeater modules removal provided convenience for designers to do LEC. Aug 2004 – Oct 2011 Cadence Design Systems, Inc. San Jose, CA Member of Consulting Staff

Designed and developed next generation of SoC Encounter/Innovus floor-planning production software

Developed new algorithms to improve by 20x the runtime of ILM/PAC flows using C/C++

Designed and implemented new methodologies in hierarchical flows using ILM, so that ILM could be switched between interface-logic-only model and .lib model

Enabled ILM definition to be loaded by demand at any time of the flow for different design stages, such as floor- planning, placement, routing, optimization, timing analysis, clock tree synthesis and signoff o Applied ILM models to MMMC and low power flows

Supported low power hierarchical flows

o Suggested using hierarchical modeling for digital and analog mixed-signal designs o Provided new ideas to improve Nano-Route, such as new algorithms to enhance global-route and detailed- route

Enhanced partitioning and design assembly to meet the challenge of multi-level hierarchy, rotated or misaligned partition blocks

o Created the infrastructure of black blob of which the property could be changed based on the designers’ needs

Developed application software that applied different kinds of hierarchical models, such as ILM, black-blob, black- box, partition for advanced prototyping, implementation and timing closure

Developed Encounter flow scripts and data for PE’s and PV’s o Helped establish Encounter’s physical design foundation flows and scripting o Documented the functionalities for hierarchical and prototyping flows o Presented the documentations among different groups

Worked on the project, First Encounter integration with OA prototyping o Discovered the mapping between First Encounter database and OA database o Derived common APIs that could access both databases o Used these APIs to re-implement First Encounter’s GUI code such that First Encounter could render OA’s objects directly

o Analyzed the performance of this prototype version of Encounter to provide a direction on how First Encounter integrates with OA, such as how to interact between Virtuoso and First Encounter May 2000 – Aug 2004 Synopsys Inc. (formerly Avanti Corp., acquired in 2001), Mountain View, CA Senior R&D Engineer

Designed and developed efficient and stable IC design floor-planning software tools, Jupiter/Astro

Enhanced the product Milkyway common database for IC design tools, making it possible that all Synopsys IC design tools worked more efficiently in a stable platform

Designed and developed projects for data preparation and library integration o Developed tools to read and check the challenging deep sub-micron design and electromigration rules

Translated and integrated among different formats between physical library and design data, LEF/DEF, TF/FRAM, PLIB/PDEF

o Provided database and tool independent APIs to logical synthesis and physical implementation tools development

Continuously designed physical library modeling for new technology requirements and implemented all new object models to schemata, providing better capacity and backward and forward compatibility Page 4 of 5

Improved the locking/unlocking mechanism of libraries and cells for timing driven place and route tools enabling multiple users access to the same database, data loading and saving over the network faster

Implemented and maintained the schema creation for dynamic objects/attributes of design data that included formats for different purposes

o Enhanced Jupiter for pin assignment and optimization in design planning

Maintained and improved the hierarchical netlist flattener that enabled breaking down the hierarchical design to flat design for placement and routing and hierarchical timing

Designed and developed a GUI application that provided a spreadsheet-like interface in the Unix platform for design planning tools with artificial intelligence about IP-reuse

Re-implemented the netlist expanding and binding code by 2x performance improvement 1998 – 1999 The Lawrence Berkeley National Laboratory, Berkeley, CA Student Researcher and Programmer

Worked on a team to redesign and implement an application for 3-D medical images analysis, called “Scilimage” using C language, improving it with faster speed and more user-friendly GUI

Analyzed multi-dimensional medical images using the Scilimage software that as developed o Presented the collected data using MS-Excel

TOOLS & SKILLS

SoC, ASIC physical design from RTL to GDS with best PPA and EM/IR results

Low power place and route, RTL, Verilog and low latency/low skew clock tree methodology and design

Multi-hierarchical floor-plan, low-power power grid, power distribution management

Place and route, scan insertion and optimize ASIC designs to achieve efficient power, high performance in smallest size

IR-drop, EM, power and timing closure and signoff for high frequency designs with custom hand placement of logic for better PPA

VLSI ASIC designs, static timing analysis, ir-drop, EM, power analysis, extraction and physical verification

FinFET, planar semiconductor modeling, ATPG, Liberty, DEF/LEF and SPEF

Leading-edge fusion technologies for EDA, electronic designs and advanced semiconductor processes.

FinFET and beyond semiconductor technologies and quantum spintronics computing and high-performance computing

Design Compiler, ICC2/ICC, DC, F2B, Innovus, RedHawk, Prime-Time, Star-RC, VCS, Encounter, ICV, IC- Workbench, Calibre, Custom-Compiler, MATLAB

VLSI architectures and design methodologies, FPGA

Firmware, embedded programming, field system engineering

Microprocessors, embedded memories, controls, interconnect, DDR, I/Os and computing architectures

RTOS and other operation systems, hardware, firmware, software architectures and computing layers managements

SSD, PCIe, NVMe, SRAMs, ROMs, DRAM, flash, register files, eMRam, TCAM

DSP, transmitters, receivers, digital and analog contents transfer and protocols

Object oriented programming, assembly, Lua, C/C++, Python, Tcl, Perl, Java, C#, Simpl, kernel scripting

Parallel programming and automating methodologies to improve design turn-around times

Consumer electronic, power supplies and power efficiency, CPU/GPU/TPU

Audio, video, digital conferencing, networks field system engineering

Automotive safety and reliability standards, ISO 26262, FDA, IEC 61508

Creative thinking, agile and lean mindset, elegant works, fast learner, efficient communication and teamwork oriented

ASIC logical and physical synthesis, RTL, place and route, dynamic and static IR drop analysis, and static timing analysis

Multi-hierarchical low-power designs

7nm, 10nm, 12nm and other semiconductor technologies designs and tape-outs

VLSI architectures and design methodologies, FPGA

Computing, memories and processors architectures, RISC and x86 architectures

C/C++, Tcl/TK, Python AI Libraries, Unix shells, Perl, Sed, Awk, Java AI Libraries, xv(X-window viewer), EDA tools, such as Encounter, IC Compiler II, Star-RC, Primetime, Design Compiler, RedHawk, IC Validater, Milkyway, Library Compiler, Calibre, VCS Simulation

Fast algorithms, C/C++, Tcl, assembly language, parallel computing, shortest path, minimum spanning tree, big data.

Linux Kernel and subsystems, real time OS, Windows, MacOS, iOS, Android

Software analysis tools: Valgrind, Purify, Quantify PureCoverage and Profilers, collector Page 5 of 5

Strong creativities and communication skills

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