Mr. Debaditya Bhattacharjee

(U.S. Citizen)

Current Address:

**** ****** *****

San Jose, CA 95129

585-***-**** (C)

E-mail: ad4i6g@r.postjobfree.com

Job Objective: a position in the field of integrated circuits, preferably circuit design.

Work Experience:

12/04-present: Various positions as teacher and tutor in field of education, CA

Afficient Academy, C2 Education, ACEPrep, self, offer academic assistance in mathematics and science for students of varying ages.

5/04-11/04: Credence Systems, Milpitas, CA

Hardware Design Engineer, characterized CMOS I/O buffers and comparator. Performed simulations using HSPICE and Spectre, schematic capture, layout with Cadence Virtuoso, and layout verification (contract position).

1/00-4/03: National Semiconductor, Santa Clara, CA

Design Engineer, worked on design of ESD circuits and CMOS I/O buffers; tasks included circuit simulation with HSPICE and Star-Sim, layout with Cadence Virtuoso, verification(using Cadence, Synopsys, and Mentor Graphics CAD tools), and measurements. Projects included design and development of test chips and redesign of cell libraries to improve ESD performance. Oversaw six test chips through entire production cycle, from design to fabrication; became familiar with IC design flow. VLSI and UVM experience.

8/98-1/00: Seagate Technology, Scotts Valley, CA

Sr. Advisory Development Engineer, developed SPICE models of CMOS SCSI transceivers using HSPICE. Performed bench testing of transceivers in lab. Other projects included PCB design, some FPGA.

3/98-7/98: Avanti Corporation, Fremont, CA

Applications Engineer, supported circuit simulation software (HSPICE and Star-Sim) and addressed customer questions about circuit simulation software.

6/97-2/98: Integrated Device Technology, Santa Clara, CA

Design Engineer, redesigned CMOS circuits to meet timing specifications; used HSPICE for simulations.

11/95-9/96: TRW, Redondo Beach, CA

Analog Circuit Designer, performed design-related tasks, including schematic entry and capture, circuit simulation using HSPICE, current density analysis, layout verification (with Mentor Graphics CAD tool).

Education:

University of Southern California, Los Angeles, CA

1991-95, M.S. in Electrical Engineering with emphasis in Integrated Circuits received 5/93.

Completed two more years of graduate school.

Rochester Institute of Technology, Rochester, NY

1985-90, B.S. in Electrical Engineering received 2/90.

CAD Tools:

HSPICE, Spectre, Cadence Opus, Analog Artist, Diva (DRC and LVS), Star-Sim, Hercules (DRC and LVS), Dracula, Verilog

Measurement Tools:

Oscilloscopes, Digital multimeters, Semiconductor parameter analyzers, Wafer probers, Signal generators, Power supplies, Ohmmeters

Circuit Design Projects

I. Projects done at USC

A. Spring 1992

1. EE533a

a. Designed CMOS Operational Amplifier

2. EE536

a. Performed analysis of nine bipolar cells

B. Fall 1992

1. EE447L

a. Designed and built functional weather station (with one partner)

-performed four functions

2. EE577a

a. Designed and performed layout of circuit to tally number of ones in

a three-bit input

b. Designed and laid out ring oscillator

c. Designed and laid out three stage barrel shifter

d. Designed and laid out Finite State Machine

C. Spring 1994

1. EE577b

a. Collaborated with four other people to design and create layout of D/A converter

and FIR filter

-my responsibility was operational amplifier

D. Fall 1994

1. EE448

a. Designed RF Bandpass Filter (with one partner)

II. Projects done at TRW

A. Sigma-Delta Modulator

1. Worked on schematics and layout

2. Performed dc operating point analysis

3. Performed LVS checks

B. Advanced Monolithic A/D Converter

1. Performed current density analysis to ensure that resistors and

metallization lines did not transgress current density specifications

2. Performed bus drop analysis to ensure that voltage drop along

metallization lines wasn’t excessive

C. I/Q Modulator

1. Performed FFT analysis of circuit

D. FFD-4

1. Performed failure analysis of voltage reference and buffer

2. Performed current density analysis of entire chip

E. GST-2 Standard Cell Library

1. Simulated cells to determine worst-case propagation delay

2. Simulated flip-flops and latches to measure setup and hold times

III. Projects done at IDT

A. Redesigned I/O buffers to meet timing and noise specifications.

1. Studied circuit layout to extract parasitic resistances and

created more realistic circuit model, performed noise simulations

IV. Work done at Avanti

A. Solved tough technical problems customers had with HSPICE

1. Discerned cause of "timestep too small" and dc convergence errors.

2. Wrote internal technical paper on causes and methods of correcting

such errors.

V. Projects done at Seagate

A. Building analog models of SCSI transceivers and transmission lines.

B. Performing parametric tests on transceivers and cables, and correlating

experimental results with simulation results.

C. Writing technical papers on results of analysis.

VI. Projects done at National Semiconductor

A. Development of SPICE models for the simulation of snap-back phenomenon in transistors.

B. Layout and verification, including DRC, LVS, and antenna analysis, of I/O libraries

C. Design and verification and bench testing of test chips

1.Designed test chip consisting of I/O cells and ESD protection circuits

2.Created schematic and layout of test chip

3.Performed verification of test chip layouts

4.Executed steps leading to tapeout, including layer generation

5.Submitted fracture form for fabrication of design

6.Had fabricated wafers assembled into individual parts

7.Submitted parts for ESD stressing and performed bench testing on parts

D. ESD evaluation of I/O libraries

Skills acquired:

Simulation with Cadence tools

Behavioral modelling of analog and mixed-mode circuits

Layout supervision and verification

Preparation of test plan

Product characterization

Bench evaluation both at the silicon level and application level

Design documentation

Validation

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