Digital Design Engineering student for FPGA/ASIC/SoC

Duval MAMBOU

FPGA /ASIC Design Engineering Student

LinkedIn: https://www.linkedin.com/in/duval-mambou/ Email: ***********@*****.*** Phone: +33 7 48 54 39 91 Location: 5 avenue de Tarente Brest, France. Available to relocate to Canada OBJECTIVE

Final-year Master’s student (M.Sc.) in Electronics and Embedded Systems seeking a 6-month FPGA Development Internship. Strong interest in FPGA RTL design and verification, with hands-on experience in IP core development, simulation, timing analysis, and FPGA validation. Expected graduation: October 2026. KEY PROJECTS

UART-FIFO Interface IP Core with Avalon-MM Bus Integration Verilog, Quartus, TimeQuest, System Console

Designed complete RTL datapath and control logic for UART-FIFO communication

Implemented address decoding, register-based configuration, and interrupt management

Performed RTL simulation and timing analysis to achieve timing closure

Integrated the IP as a peripheral in a full System-on-Chip environment and validated on FPGA hardware PWM Generator IP for FPGA-Based Control Applications VHDL, ModelSim, TCL

Designed an RTL datapath for carrier-based PWM generation with programmable period and duty cycle

Implemented register-controlled configuration with synchronous updates

Used shadow registers to guarantee glitch-free parameter changes at period boundaries

Verified correct behavior through RTL simulation and timing analysis Real-Time Clock (RTC) Module on Cyclone V FPGA VHDL, Quartus, QSys, ModelSim, TCL

Defined a complete RTL architecture including control logic, register map, and clocked state machines

Implemented synthesizable VHDL with synchronous logic, reset strategy, and register-based configuration

Developed simulation testbenches to verify functional behavior and corner cases

Developed C-based API for software control and created Tcl test scripts for unit and full system testing

Validated all timing functions and alarm triggers on DE0-CV FPGA with C-based test application PROFESSIONAL EXPERIENCE

Electronics & Embedded Software Engineering Intern March – August 2025 (6 months) TEKIN SAS, Tours, France

Project: Embedded system development for railway catenary cable wear inspection drone

Developed C /C++ real-time embedded software with UART, I2C, SPI, DMA-based data streaming

Worked on system-level validation and hardware/software interaction

Collaborated on performance-critical data acquisition pipelines Embedded Systems Technician Intern August – October 2022 (2 months) EstEnLigne, Bonabéri, Cameroon

Project: Electronic system design for electrical power outage detection

Developed embedded software in C with version control using Git

Tested and validated system functionality under various power conditions EDUCATION

Master of Science, Electronics & Embedded Systems September 2023 – September 2026 National School of Engineering of Brest (ENIB-Bretagne INP), Brest, France Specialization: System-on-Chip (SoC) Design

Master’s Degree, Management and Business Administration September 2024 – September 2026 Institute of Business Administration (IAE-Bretagne INP), Brest, France Dual Degree Program – Engineering & Management

SKILLS

Languages: VHDL, Verilog, C, C++, TCL, Python, Matlab, Assembly. Tools: ModelSim, Quartus, Git/GitHub/GitLab, STM32CubeIDE, NXP, MCUXpresso, KiCad, MATLAB, ADS Communication protocols: UART, I2C, SPI, CAN, OpenAMP, Ethernet, UDP, Modbus TCP, BLE, Zigbee. Methods: RTL design, simulation & verification, FPGA prototyping, timing analysis, test and validation LANGUAGES

French: Native English: Fluent (B2 - Professional working proficiency) German: Basics (A1) - Learning

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