Digital Design Rtl

Rafath Achugatla

Portland, OR ***** Mobile: +1-971-***-**** E-Mail: ******@***.*** LinkedIn

OBJECTIVE

Actively Seeking internships in Digital Design and Verification starting January 2025. EDUCATION

Master of Science: Electrical and Computer Engineering GPA: 3.84/4.0 Portland State University, Portland, Oregon. (Jan 2024 – Mar 2026) Relevant Coursework: Microprocessor System Design, System Verilog, Fund of Pre-Silicon Validation, Computer Architecture, Adv Computer Architecture, Assertion Based Verification, Python & Scripting WKSP. Bachelor of Engineering: Electronics and Communication GPA: 3.70/4.0 Sree Vidyanikethan Engineering College, Tirupati, India. (Jun 2017 – May 2021) TECHNICAL SKILLS

Languages : Verilog, SystemVerilog, C, Python, Perl(Basics). Methodology : Universal Verification Methodology (UVM). Design/Verification Skills : RTL Design, SV Testbench, Constraints, Randomization, Assertions, Coverage, OOPS Concepts : DRAM, Caches and Coherence Protocols, Pipeline, Branch Prediction Protocols : AMBA AHB 3 lite, AMBA APB, MESI, MESIF Tools : ModelSim, QuestaSim, Xilinx Vivado, Synopsys VC Formal and GitHub ACADEMIC PROJECT

[UVM, SystemVerilog] UVM environment-based verification of Asynchronous FIFO

• Designed a synthesizable RTL for asynchronous FIFO.

• Developed a verification plan and implemented components such as generators, drivers, monitors, scoreboards, and checkers to verify the design using class-based and UVM-based verification techniques.

[UVM, SystemVerilog] Functional Verification of APB Protocol

• Prepared a verification plan to verify the functionality of the APB protocol.

• Developed components like Generator, Driver, Monitor, Scoreboard, and Environment.

[SystemVerilog] Simulation of DDR5 Memory Controller Scheduling Algorithm

• Simulated a DDR5 memory controller for a 12-core 4.8 GHz processor with a 16GB PC5-38400 DIMM.

• Implemented open-page policy and out of order scheduling, issuing DRAM commands and validating with test cases.

[SystemVerilog] Simulation of Level 1 Split Cache with MESI protocol and LRU

• Simulated a Split L1 Cache for a 32-bit processor in a shared memory configuration, implementing the MESI protocol to ensure coherency.

• Implemented Counter Based LRU policy for block replacement during evictions and reported statistics.

[SystemVerilog] Transaction/Bus Functional Modeling of Intel 8088 Bus

• Simulated and implemented an interface for the Intel 8088 microprocessor, focusing on bus protocol and timing.

• Designed memory and I/O blocks and verified 8088 timing parameters.

[SystemVerilog][Assertions] Design and Verification of leading zero detectors, Arbiter

• Designed different leading zero detectors(LZD) variants like combinational LZD, Pipeline LZD, FSM-based LZD modules, and Arbiter.

• Developed exhaustive self-checking testbenches for the mentioned designs and wrote assertions to verify the Arbiter. TECHNICAL TRAINING

Maven Silicon: Advanced VLSI Design and Verification Trainee, Bangalore, India (Apr 2022 – May 2023)

• Designed 1*3 Router and Developed the architecture of block level structure for the design.

• Implemented RTL using Verilog and followed bottom up design methodology.

Contact this candidate