Design Verification Internship Opportunities

Brunda Marpadaga

503-***-**** ******@***.*** linkedin.com/in/brundamarpadaga github.com/brundamarpadaga Objective

Looking for Internship opportunities in Design Verification/ Computer Architecture starting May 2025. Education

Portland State University, Portland, OR Jan. 2024 – December 2025 Masters in Electrical and Computer Engineering GPA: 3.94/4

• Coursework : Microprocessor System Design, Introduction to SystemVerilog, Computer Architecture, Pre-Silicon Validation, Introduction to Python Scripting, SOC Design with FPGAs, Assertion Based Verification, Embedded Design with FPGAs, Formal Verification of Hw/Sw systems Vasavi College of Engineering, Hyderabad,TS,India Oct. 2020 – June 2023 Bachelor of Engineering in Electronics and Communications GPA: 3.37/4 Government Institute of Electronics, Hyderabad,TS,India June 2016 – December 2019 Special Diploma in Embedded Systems GPA: 3.7/4

Technical Skills

Languages: SystemVerilog, Matlab, Java, Python, C/C++, Embedded C Scripting Languages: Python, TCL

Assembly Languages: 8086, 8051, ARM Cortex-M4, PIC, RISC-V, MIPS Methodologies: UVM, Agile Protocols: I2C, Wishbone, UART, SPI

Concepts: Data Structures, Digital Logic Design, System Verilog Assertions, Randomization and Constraints, Environment-based Verification, Coverage-Driven Verification, Code/ Functional Coverage, Scoreboards, OOPS, Static Timing Analysis, DDR Memory, Caches, Cache Coherence, Virtual Memory, MESI, MOESI, MESIF, Pipelining, Scheduling, Branch Prediction, Formal Verification Test Equipment: Oscilloscope, Voltmeter, Logic Analyzer Tools: Questasim, Xilinx Vivado, MentorGraphics, PSpice, and VCFormal Projects

Design and Verification of Asynchronous FIFO SystemVerilog, UVM April 2024 – June 2024

• RTL design for FIFO aiming for asynchronous read and write. Prepared test plan and designed test bench.

• Implemented synchronizers and used gray code pointers to reduce the probability of metastable states.

• Testbench created with UVM architecture. Constrained randomized tests with full functional coverage. Simulation of Scheduler portion of Memory Controller C Language January 2024 –March 2024

• Implemented the scheduler portion of the Memory Controller that schedules the memory requests that are in the input trace file

• Implemented open page policy for DDR 5 Memory Module that generates DRAM commands without any Timing Violations

8088 interfacing with the Memory and IO modules SystemVerilog Jan 2024 – March 2024

• Implemented the bus interface of 8088 with memory and IO module using interfaces, bus-functional models, FSM modeling

Design of Pipelined processor for MIPS architecture SystemVerilog April 2024 – June 2024

• Simulated the behavior of MIPS architecture without pipeline and with 5-stage pipeline (forwarding and without forwarding)

• Compared the speed-up achieved by forwarding and without forwarding Design of Cache Controller using MESI protocol SystemVerilog April 2024 – June 2024

• Simulated the behavior of cache controller for 32-bit processor backed by L2 by maintaining inclusivity.

• Write back and write allocate policies used, True LRU eviction to replace blocks and MESI to maintain coherence. Experience

Camp Counselor July 2024 - August 2024

CyberPDX: A Cybersecurity Camp for Native & Indigenous High School Students Portland,OR,U.S.

• Mentored and supervised a group of Native and Indigenous high school students during a 5-day residential STEAM camp focused on CyberSecurity, Generative AI, Computer Science, and related fields.

• Led and facilitated interactive STEM activities, helping students explore cybersecurity concepts through a multidisciplinary curriculum that included computer science, arts, and literature. Full Stack Engineer July 2023 – December 2023

Prodapt IT Solutions Hyderabad, TS, India

• Skills : SpringBoot, MongoDB, SQL, AngularJS, Git, Docker, Agile, Waterfall Methodology, Jira, Linux

• Developed a full-stack web application ”Analytics-Dashboard (Telecommunication)” using SpringBoot and MongoDB

Failure Analysis Intern May 2019 - Dec 2019

Electronics Corporation of India Limited [ECIL] Hyderabad, TS, India

• Skills : Visual-Inspection, Functional Testing, In-Circuit Testing [ICT], EMI/EMC Testing, Trouble-shooting

• Collaborated with the manufacturing team to identify failures, implement corrective actions, and enhance yield rates.

• The assigned responsibilities covered multiple stages of production line, including Visual-Inspection, Debugging, Functional Testing, In-Circuit Testing, and Calibration of Smart Energy Meters. Training/Certifications

Basic Static Timing Analysis v3.0 September 2024

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