Embedded Engineer

Tran Huy Hoang

081******* *****.*************@*****.***.** www.linkedin.com/in/huy-hoang-tran

Thu Duc District, Ho Chi Minh City

EDUCATION

Hoang Van Thu High School 2018 - 2021

9.0/10 for total

Natural Science Specialized class

Ho Chi Minh City University of Technology (HCMUT) 2021 - 2025 (expected) Faculty of Electrical and Electronics Engineering

Major: Electronics and Telecommunications Engineering Direction: IC Design

GPA: 2.5/4 for 6 periods

CERTIFICATIONS

TOEIC Listening and Reading for 740 points 6/2024

SKILL

Programming language C#,Python, Assembly, Verilog, Matlab Simulation Proteus, Matlab, LT Spice, Quartus

Chip design tool CADENCE DESIGN SYSTEM, LTSpice XVIII Electrical Skills Basic knowledge of electrical and electronic devices Office skills Word, Excel, Powerpoint

English Good written, reading, listening and verbal comunication in English OBJECTIVE

Short-term

Get TOEIC Speaking and Writting for 250 points by 2024 Graduate with GPA 7.0/10 in 2025

Work as IC Design Engineer after graduation

Long-term

Continuing commitment to the microchip industry

Become Principal Design Engineer in 10 years

PROJECT

PROJECT 1: DESIGN NANOELECTROMECHANICAL

( 1/2024 - 5/2024 )

Customer Teacher

Description Project Design Nanoelectromechanical using LTSpice XVIII Teamsize 2

My position Frontend Developer

Responsibility in Project

Searching for theorectical basic

Creating component

Run simulation

Technology Description LTSpice XVIII, Cadence Design System Tools, Matlab PROJECT 2: STANDARD CELLS

( 4/2024 - 4/2024 )

Customer Team

Description Project Implement Logic Gate using CMOS technology: NAND, NOR, AND,OR Teamsize 5

My position Developer, Tester

Responsibility in Project

Complete the truth table, schematic, symbol and layout for each component Run DC analysis and transient simulation

Check DRC and LVS

Technology Description Cadence Design System Tools PROJECT 3: ANALOG AND MIX SIGNAL CIRCUIT DESIGN

( 4/2024 - 4/2024 )

Customer Team

Descripton project

I/V characteristics of NMOS transistor Consider the CMOS single-stage amplifier: Common source stage with resistive load Analyze and design basic Sample and Hold circuit

Teamsize 5

My position Developer, Tester

Responsibility in Project

Consider ID/VDS characteristics of NMOS

Considering the Transient Response of the Amplifier to a Sinusoidal Input Voltage Design of a Basic Sample and Hold Circuit

Technology description Cadence Design System Tools HONORS & AWARDS

4th place in Provincial Science and Engineering Fair 2018 3th place in Provincial Science and Engineering Fair 2020

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