Electrical Engineering Student at RIT
Resume:
START Collin Neidel
RIT Electrical Engineering
About
Projected Graduation Date:
May 2025. Open to relocation.
Areas of specialization
Computer Architecture • RTL
• Digital Verification • FPGA
• Micro-controllers
Leadership
Teaching Assistant • Circuits I
(Fall 2023 + Fall 2024)
• Digital Systems II
(Fall 2022 + Spring 2024)
• Design of Digital Systems
(Spring 2025)
Secretary • RIT Jam Club
(Spring 2022)
Project Manager • Eagle
Scout Project
(Summer 2019)
Memberships
ResearchGate Member
(July 2024–Present)
RIT Men’s Club Volleyball
(Aug 2020–Present)
RIT Jam (Music) Club
(Aug 2021–Nov 2023)
National Honor Society
(2016–2020)
Boy Scouts of America (BSA)
(2015–2019)
Awards
Dean’s List
(2020–Present)
Presidential Scholar
(2020–Present)
Recognition Scholar
(2020–Present)
BSA Eagle Scout Rank
Oct 2019
Interests
Volleyball • Buffalo Sports
• Music • Personal Mini
Projects • MTG TCG
Q *******@***.***
Lancaster, NY
in Collin Neidel
EXPERIENCE
May 2024–Aug 2024 Electrical Engineer Intern
MOOG INC. · East Aurora, NY
Provided engineering support for Circuit Card Assembly (CCA) level test development for military aircraft flight control systems. Included reviewing testing requirements and ensuring they are implemented into test stand software. Gained an understanding of process and production flow, as well as how to write clear and concise work instructions. Tools used: Cirris Easy-Wire, Python, Microsoft Excel and Visio Jan 2023–Aug 2023 Controls and Electronics Engineer Intern PLUG POWER · Henrietta, NY
Developed and implemented safety control systems to prevent putting both products and operators in danger. Obtained a deep understanding of the OEM products used in test stands and how they fit into the larger system, by reading documentation and debugging. Learned how to build electrical enclosures, spec out parts, and understand control schematics. Tools used: Beckhoff TwinCAT 3, Banner Safety SW, TCP/IP, CANopen EDUCATION
2020–2025 Electrical Engineering
BS/MS · Rochester Insti-
tute of Technology
3.870 Cumulative GPA
MAY 2025 · Graduation
TECHNICAL SKILLS
SW Vim, Perl/Python, SystemVerilog/UVM,
Synopsis, ModelSim, Lyx/LaTex, Ca-
dence tools, Cirris Easy-Wire, TwinCAT 3,
Banner Safety Software, TCP, CANopen,
Verilog/VHDL, MATLAB, Assembly,
SPICE, C/C++, Arduino IDE, Intel Quar-
tus Prime, Ladder Logic.
HW Altera/Intel FPGAs, TI microcontrollers,
Banner, Beckhoff, and CLICK PLCs, Os-
cilloscope, Digital Multimeter, Function
Generator, Network Analyzer, Crimping
tools, Soldering tools, and Breadboard.
PROJECTS
Jan 2024–Apr 2024 Design of Digital Systems Projects GLE · RIT
Developed a CMOS standard cell library with Cadence tools. Cells were designed at transistor level with custom layouts and were used in hierar- chical design/place and route characterization of 16-bit carry select adder with 50 boundary scan cells attached for built-in test. Project specs: 180 nm W, 45 nm L, 2x drive strength INV, AOI, CMOS MUX Aug 2024–Dec 2024 Complex Digital System Verification Projects GLE · RIT
Developed a fully parameterized code generator in Perl, and then again in Python to produce synthesizable Verilog RTL and a companion verification testbench in Verilog based on a user provided configuration. Addition- ally, developed a full featured verification environment in SystemVerilog and SystemVerilog DPI, and then again using the UVM library and UVM Methodology. Testbench features include: assertions, coverage, and ver- ification based on a fully automatic methodology by including reference models coded in C and C++.
Project specs: Full-Scan DFT ports, Self checking, Time DPI Functions Aug 2024–Dec 2024 Design of Computer Systems Projects GLE · RIT
Designed a RISC core in Verilog HDL based on unique specifications and a Inter Core Communication Protocol. The core was implemented with a 4-Way associative, level 1 cache with 16 block locations and 8 words block size. It was also functionally verified and flashed to a DE0-Nano FPGA in 1, 2, and 4 core configurations. Additionally, an assembler was developed from scratch in Perl that writes a MC file based on ASM code input. Project specs: 14-bit Word Size, Von Neumann, Separate Mapped I/O-Ps
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