Project Design

gauGaurav Mane

Mobile :+918*********

Email :************@*****.***

Address for Correspondence:

Yash-Laxmi, bld,

Kasarwadi,Pune-411034

Completed M.TECH in VLSI DESIGN from VIT University ,Vellore, Tamil Nadu. Waiting for Semester-4 result.

Class Board Year Marks

MTECH VIT University 2010-12 7.77 /10

B. E. Instrumentation Engineering Pune University 2009 66.96

XIIth Maharashtra Board 2005 65.33

Xth Maharashtra Board 2003 70.40

MTECH Final Year project :

Project Name Implementation of Multi-mode OFDM transmitter using partial reconfiguration on FPGA

Tools ,language and Hardware Xilinx 12.3ise, Plan Ahead 12.3.ise, VHDL, Virtex-5 board.

Duration (9 months i.e September 2011 to first week of May 2012)

Description Implementation of Multi-mode OFDM transmitter on same FPGA due to advantage of reconfiguration possible in FPGA. Design consists of static portion and reconfigurable portion. Partition will be created inside FPGA for reconfigurable portion so that Reconfigurable portion will reside in that area. Based on application that portion can be configured (ex. 8 point IFFT will later be configured to 16 point IFFT in same portion). Scale down model for multi-mode OFDM transmitter has been practically implemented on vertex-5(LX110T-1ff11136) FPGA. Advantage of Partial Reconfiguration is reduce in time taken to configure the FPGA. Other advantage of Partial Reconfiguration is that it allows user to reconfigure the part of same FPGA while other application is running on same FPGA.

ASIC Mini project :

Project Name “Synchronous square root generator ”

Tool RTL Compiler (front end) , SOC Encounter (back end) by Cadence

Duration 3 Months

Description Design of Synchronous square root generator is done on given specifications. RTL code is synthesis using RTL compiler. Prelayout netlist is generated by using RTL compiler and then simulated to check the functionality of design . Similarly Post layout netlist is generated using SOC Encounter and functionality is verified for post layout netlist using RTL Compiler.

Title: Condition Monitoring For Extending Oil Filter Change Periods.

Sponsored by –Kirloskar Oil Engine LTD, Khadaki, Pune - 03

Introduction :

It is based on monitoring pressure drop across oil filter and informing the user about filter change period through SMS and also to display the differential pressure on LCD display. Thus helps in bringing down the maintenances cost of oil filter & increase in life span of oil filter.

Tools :

• Design Architect by Mentor-graphics

• RTL Compiler (front end) , SOC Encounter (back end) by Cadence

• Xilinx ISE 12.3i

• Plan Ahead Xilinx 12.3i

Languages : Verilog, VHDL.

Operating Systems : LINUX, Windows.

ASIC Design.

FPGA.

Digital Design

Engineering Trainee, Application Engineering,

Kirloskar Oil Engines Ltd, Khadaki, Pune.

Duration 02nd November 2009 to 06th July2010.

Key Responsibilities

Worked on Gas Engines.

Involved into Implementation of new Genset controllers & remote monitoring project.

Panel design.

Date of Birth : 04– 02 –1987

Nationality : Indian

Languages known : English, Marathi, Hindi.

Hobbies : Playing Cricket, Trekking, Chess.

Permanent Address : Yash-laxmi, Mane Bld, Kasarwadi, Pune-411034

REFERENCES:

1. V.Arunachalam

Sr.Assistant Professor(SG) ,

School of Electronics Engineering,

VIT University,

Tamil Nadu, India

E-Mail: ************@***.**.**

2. K.Sivasankaran

Assistant Professor (Sr),

School of Electronics Engineering,

VIT University,

Tamil Nadu, India

E-Mail: *************@***.**.**

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