Design Engineer

CURRICULUM VITAE

PUNEET SHARMA

H.No.*, New Karhera colony,

Mohannagar, Ghaziabad

Contact No.: +91-830*******

E-mail:******.**********@*****.***

Objective: To work efficiently and diligently as per the requirement of job with exploring every possible opportunity to learn new productive things.

Current Company: Project Engineer in Wipro Technologies (VLSI)

Experience: 1 year

Technical skills:

●RTL Design and Verification using below mentioned tools and processes:

Simulation: NCSIM (Cadence), IUS (Cadence)

●Design Convention Check, Design Constraints Check and Clock Reset Check (Linting): Spyglass (Atrenta) and Leda (Synopsis)

●G2G and R2G Logical Equivalence Check using Encounter Conformal EC(Cadence)

●Synthesis: Design Compiler (Synopsys)

● Module level functional verification on Simvision (Cadence) and top level functional verification on nWave (Novas).

Programming Languages: Verilog, VHDL, UNIX, C

Projects in Wipro:

• PMIC: Power Management Integrated Circuit (PMIC) for mobile application processors platforms with high feature integration in order to minimize system board area. It includes subsystems for voltage regulation, A/D conversion, GPIOs and RTC. There is a Serial Voltage ID interface between the SOC and PMIC for handling Core voltage rail settings as well as system control signals. It is a project of Texas Instruments, which has been awarded to them by Intel.

My Role in it: I manage a whole Module called SVID (Serial Voltage ID), which is the heart of the project, apart from giving assistances to different subgroups in their technical doubts clarification regarding the specifications and design.

• MDIO (Management data input output): It is a serial bus defined for the Ethernet family of IEEE 802.3 standards for the Media Independent Interface. The MII connects Media Access Control (MAC) devices with Ethernet physical layer (PHY) circuits.

My Role in it: I made the slave part of the MDIO completely, while Master part was made by my colleague. Linting, Synthesis and Code Coverage were also done by me.

• I have also made several mini projects like Arbiter, General purpose input output (GPIO), Vectored interrupt manager (VIM), etc.

Projects in College:

• Stop Watch: Implemented stopwatch code on FPGA. Coding of the stopwatch was done in the Verilog Language. It could count up to 999. It had many modules, namely, a 1 sec pulse timer,4 bit up/down counter, which was used in a 12 bit counter, trigger detection module and seven segment displays.

• Traffic Light controller and implemented it on FPGA in VHDL

• Cyclic redundancy Check (CRC) using arithmetic-modulo algorithm in VHDL

Trainings:

• Have undergone training of Vlsi in Wipro Technologies for 3 months on Verilog, Digital design logics, FPGA, Memories, Microprocessors, Static timing analysis, Gate level simulation, Unix, Code coverage, Linting, Synthesis etc., and have made several mini projects like Arbiter, General purpose input output (GPIO), Vectored interrupt manager (VIM), etc.

• Undergone training in VHDL programming from ECE Department Society during 2008-09.

Paper presentations:

• Count ability of Rational Numbers

Description: Set of rational numbers is countable like set of natural numbers, which means that we can count things by using rational numbers similar in the way as we do in case of integers. Furthermore, with the help of rational numbers, we can simply count 10 entities with 4 numbers(1,2,3,4) ; 15 with 5 numbers(1,2,3,4,5) and so on. Hence we can see that this simple result of count ability leads to a major outcome i.e., data compression.

• Compressed RAM for Embedded Systems

Description: It is based on data compression technique which reduces the size of data present on RAM by 60% at a blazing speed and is more efficient than the previously accepted techniques like LZ78 and LZW. The striking feature of this technique is that here we needn’t to store the dictionary in memory in advance and is produced simultaneously as the data processes, thereby negating the need of memory for dictionary storage in RAM.

Scholastic achievements:

• Secured 97.36 percentile (2nd position) in VHDL test organized by ECE Society.

• Received Scholarship from U.N.E.S.C.O. (pre-senior UNESCO Information Test) at school.

Awards and Felicitations:

• Won 1st position in Paper presentation in Prayas’08.

• Won 1st position in Bizbuzz (business plan presentation) in techsrijan’09.

• Won 1st position in VHDL contest.

• Won 2nd position in VHDL test.

• Won 2nd position in Techprastuti (paper presentation) in techsrijan’09.

• Won 2nd position in Spell-Czar’09(a spelling contest).

• Won 2nd position in 4x100m Relay race.

• Won 2nd position in regional level science exhibition conducted by Kendriya Vidyalaya Sangthan.

• Won consolation prize in Basketball at KNIT, Sultanpur.

• Won several prizes in essay writing, quizzes, and sports at school.

Position of responsibility:

• College Basketball team captain.

• Taught VHDL to more than 70 students of ECE as a Student Faculty.

• Head Prefect boy in School.

• Headed plantation program in School being the house captain in X class.

• NCC cadet

Personal Details:

Father’s Name: Shri V.S.Sharma

Date of Birth: 13th June, 1989

Hobby: Reading, article writing.

Additional Details:

Years of exp in FPGA Design: 1 year

Years of exp in VHDL Coding: 2 year

Years of exp in Altera / Xilinx /Actel: 1 year

Current CTC- 3.25 lacs

Expected CTC- 6 lacs

Notice Period- 1 month

Current Employer name: Wipro Technologies (VLSI)

Are you a contract employee? No

Are you willing to relocate to Bangalore? Yes

I hereby declare that the above mentioned information is true to the best of my knowledge.

(PUNEET SHARMA)

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