| Resume alert | Resumes 71 - 80 of 194 |
ASIC Design
Irvine, CA
... Familiar with Verilog/RTL coding, FPGA, DFT, lower power, hierarchical front/backend design flows/utilities. SKILLS ASIC/FPGA: Cadence: NC Verilog/Genus/CCD/Verplex-LEC&CLP/ Encounter/Platform . Synopsys: DC/DCG/Siloti/ Formality/Prime-Time/Power ... - 2018 Mar 06
... Familiar with Verilog/RTL coding, FPGA, DFT, lower power, hierarchical front/backend design flows/utilities. SKILLS ASIC/FPGA: Cadence: NC Verilog/Genus/CCD/Verplex-LEC&CLP/ Encounter/Platform . Synopsys: DC/DCG/Siloti/ Formality/Prime-Time/Power ... - 2018 Mar 06
Design Electrical Engineering
Los Angeles, CA
**** ***** ***** ****** Santa Clara CA, ***** C: 213-***-**** SAVINAYA RAJENDRA ac4mzc@r.postjobfree.com ac4mzc@r.postjobfree.com https://www.linkedin.com/in/ savinaya-rajendra-77145a133 Technical Skills Hardware Description languages: Verilog HDL ... - 2018 Feb 27
**** ***** ***** ****** Santa Clara CA, ***** C: 213-***-**** SAVINAYA RAJENDRA ac4mzc@r.postjobfree.com ac4mzc@r.postjobfree.com https://www.linkedin.com/in/ savinaya-rajendra-77145a133 Technical Skills Hardware Description languages: Verilog HDL ... - 2018 Feb 27
Engineer Microsoft Office
Los Angeles, CA
... ●Expertise in C, Python, Verilog, Unix, Spice, AutoCAD, JMP, LabVIEW and MATLAB. ●Excellent interpersonal and communication abilities and a wide range of technical skills. ●Exceptionally good at mentoring, managing, motivating, and training a ... - 2018 Jan 24
... ●Expertise in C, Python, Verilog, Unix, Spice, AutoCAD, JMP, LabVIEW and MATLAB. ●Excellent interpersonal and communication abilities and a wide range of technical skills. ●Exceptionally good at mentoring, managing, motivating, and training a ... - 2018 Jan 24
Software Engineer Full Time
Los Angeles, CA
... Instrumentation Engineering, Teaching assistant for “Modern Physics” SKILLS Programming: Java, Python, MATLAB, C++, Xilinx (Verilog),Assembly Language Web: HTML, CSS, Javascript, PHP, Responsive Web Design, AWS, AJAX, JQUERY, HTML5,Rest API, Angular ... - 2018 Jan 18
... Instrumentation Engineering, Teaching assistant for “Modern Physics” SKILLS Programming: Java, Python, MATLAB, C++, Xilinx (Verilog),Assembly Language Web: HTML, CSS, Javascript, PHP, Responsive Web Design, AWS, AJAX, JQUERY, HTML5,Rest API, Angular ... - 2018 Jan 18
ASIC Design, VLSI, RTL, Computer Engineer
Los Angeles, CA
... Completed a UNIX-like multi-threaded/ processed kernel with Virtual File-System(VFS) layer and a Virtual Memory (VM) layer in a team of 4 Asynchronous Design of Tree-structured Network-on-Chip (NoC) with FEC, USC [Verilog, SystemVerilog, modelsim] ... - 2017 Dec 04
... Completed a UNIX-like multi-threaded/ processed kernel with Virtual File-System(VFS) layer and a Virtual Memory (VM) layer in a team of 4 Asynchronous Design of Tree-structured Network-on-Chip (NoC) with FEC, USC [Verilog, SystemVerilog, modelsim] ... - 2017 Dec 04
State University Electrical Engineering
Long Beach, CA
... Verilog, Python, NesC, Assembly 80x85, Assembly 80x86 Software: AVR, Keil, LT SPICE, MATLAB, OpenCV, PSPICE, Raspbian, SCILAB, Wireshark MS Office: MS Office 2016 Access, Excel, PowerPoint, Publisher, Word Operating Systems: Mac OS X, Windows 10, ... - 2017 Dec 03
... Verilog, Python, NesC, Assembly 80x85, Assembly 80x86 Software: AVR, Keil, LT SPICE, MATLAB, OpenCV, PSPICE, Raspbian, SCILAB, Wireshark MS Office: MS Office 2016 Access, Excel, PowerPoint, Publisher, Word Operating Systems: Mac OS X, Windows 10, ... - 2017 Dec 03
Engineer Design
Torrance, CA
... CLPD, FPGA programming in Verilog HDL with Xilinx tools and work flow Electronics Engineer 09/04-04/07 Glentek, Inc., El Segundo, CA LabVIEW programming for ATE, Data Acquisition and Analysis, Measurement, Instrument Remote Control thru RS232 and ... - 2017 Oct 19
... CLPD, FPGA programming in Verilog HDL with Xilinx tools and work flow Electronics Engineer 09/04-04/07 Glentek, Inc., El Segundo, CA LabVIEW programming for ATE, Data Acquisition and Analysis, Measurement, Instrument Remote Control thru RS232 and ... - 2017 Oct 19
Engineer Software
Irvine, CA
... August 2006 SKILLS Programming language skills: C, C++, Python, Perl, java, Verilog and 8085 Assembly Language. Software: Wireshark, JTAG, LabVIEW, M-Sim Simulator, Fiddler, Selenium, JIRA, OrCAD and MS Office. Operating systems: Mac OS, Ubuntu 12.4 ... - 2017 Oct 02
... August 2006 SKILLS Programming language skills: C, C++, Python, Perl, java, Verilog and 8085 Assembly Language. Software: Wireshark, JTAG, LabVIEW, M-Sim Simulator, Fiddler, Selenium, JIRA, OrCAD and MS Office. Operating systems: Mac OS, Ubuntu 12.4 ... - 2017 Oct 02
Design Electrical Engineering
Los Angeles, CA
... Osmania University, India, B.E in Electronics and Communications Engineering (CGPA: - 3.86/4.0) Graduated: May 2015 TECHNICAL SKILLS • Languages : System Verilog, Verilog, C, C++, Python • Tools : QuestaSim, Quartus II, Matlab, Cadence Virtuoso, ... - 2017 Sep 18
... Osmania University, India, B.E in Electronics and Communications Engineering (CGPA: - 3.86/4.0) Graduated: May 2015 TECHNICAL SKILLS • Languages : System Verilog, Verilog, C, C++, Python • Tools : QuestaSim, Quartus II, Matlab, Cadence Virtuoso, ... - 2017 Sep 18
Verilog, VHDL, Python, C, C#, PL/SQL
Los Angeles, CA
... TECHNICAL SKILLS Programming Languages: Verilog, VHDL, Python, C, C#, PL/SQL Applications and Tools: ModelSim, Cadence Virtuoso, Xilinx ISE, Prime Time, Design Compiler, Conformal, Synopsys, Cadence First Encounter, .Net, Lab Windows, Kiel ACADEMIC ... - 2017 Sep 15
... TECHNICAL SKILLS Programming Languages: Verilog, VHDL, Python, C, C#, PL/SQL Applications and Tools: ModelSim, Cadence Virtuoso, Xilinx ISE, Prime Time, Design Compiler, Conformal, Synopsys, Cadence First Encounter, .Net, Lab Windows, Kiel ACADEMIC ... - 2017 Sep 15