ASIC Design, VLSI, RTL, Computer Engineer

Howard Fu

*** * **** **, *** ANGELES, CA ***** 302-***-**** *******@***.*** http://huayufu.xyz EDUCATION

University of Southern California, Los Angeles, CA GPA: 3.61 May 2018 M.S., Computer Engineering, Digital VLSI and Computer Architecture University of Delaware, Newark, DE GPA: 3.5 May 2016 B.S., Electrical Engineering, Minor in Computer Science SKILLS

Programming & Architecture

• Good understanding in Computer Architecture and Operating System

• Programming & scripting experience using TCL, Linux/UNIX Bash Shell Scripting, Python, Perl, C/C++, and Assembly

• Practical experience with Performance Analysis, Cache Coherence, Software Debugging, Embedded Programming, and Multithreaded Programming, with emphasis on code performance, stability, and maintainability VLSI/ASIC Design & Verification

• Familiar with VLSI full-custom and ASIC design process flow and methodology

• EDA tool: Cadence Virtuoso, Encounter, DC Design Compiler, ICC IC Compiler II, PT PrimeTime, ModelSim and SimVision

• Practical experience with RTL design, Synthesis, APR Place & Route, DDR3 Controller Design, SRAM Design, Power Optimization, STA Static Timing Analysis, Performance Analysis, Handshake Protocol and CDC Clock Domain Crossing WORK EXPERIENCE

Software Engineering Intern, R&D, ECO team, Synopsys [C++, Tcl, IC Compiler II, gdb, Perforce, EDA] May - August 2017

• Proposed an algorithmic and memory efficiency base layer density aware solutions for eco/spare cell placement to reduce the turnaround time by avoiding base layer density violations in earlier stage at backend design flow

• Implemented the model in the main branch of IC Compiler II on remote Unix server with version control tools and gdb in C++, tested the model with the Tcl test scripts, successfully demonstrated the correctness of the model

• Created high efficient and high accurate place-able region locating service with the visualization on ICC II HIGHLIGHTED PROJECT

Project Leader, General-Purpose 16-bit CPU Full-customize Design Project, USC [Python, Cadence Virtuoso] March - April 2017

• Designed a Full-customize 5-stage pipelined CPU, featuring 512-bit SRAM and 16-byte register file, supports add/sub, multiply, and/or, SFL/SFR, and store/load instructions and out-of-order execution in-order-completion

• Programmed frontend and backend python code for instruction decoding, hazard detection and golden result generation

• Conducted layout drawing, performed Power & Delay optimization and employed power gating and dynamic logic techniques, and achieved 3.5ns clock period and 9.3 mW power consumption in performance Digital Neuron VLSI Design Contest, USC [Cadence Virtuoso] October - December 2016

• Designed a special-purpose digital circuit that mimics a neuron; performed logic and timing verification

• Won third place in Design Contest with the area-delay product of 695 (average 7000) RELATED PROJECT

Operating System Course Project, USC [C, Multi-Threading, Linux, gdb] March - May 2017

• Created multi-threaded program using C and POSIX API, emulated the process of token bucket with the statistical summary, with the concern of mutual exclusive and deadlock

• Implemented a Linux similar operating system, Weenix in C programming language. Completed a UNIX-like multi-threaded/ processed kernel with Virtual File-System(VFS) layer and a Virtual Memory (VM) layer in a team of 4 Asynchronous Design of Tree-structured Network-on-Chip (NoC) with FEC, USC [Verilog, SystemVerilog, modelsim] March 2017

• Designed a NoC with router, arbiter, merge and hamming code module; Synthesized into gate cells with PCHB templates Music Visualizer Embedded System (SoC) Design, UD [Xilinx IDE, FPGA, EDK, SDK, VHDL, C, Python] February - May 2016

• Designed a Music Visualizer with VGA output prototyped on Spartan-6 FPGA board

• Created VHDL peripherals for fetching audio input, programmed audio processing and visualization algorithm running in ARM- based IP-core in FPGA board, and programmed controller to control Visualizer through UART port

• Empowered the FPGA board to output smooth patterns to VGA port, with two different display modes

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