Kevin A. Yang
Email: email@example.com IRVINE, CA 92603
Over 15 years hands-on experience in implementation of complex ASIC SoC designs from project kick-off, tape-out, engineering sample approval to mass production.
Play a key role as the technical leader, driving project schedule, coordinating global resources successfully on-time deliver the high performance SoC chip- up to 10GHz, lower power and 300M gates wireless baseband project.
Familiar with Verilog/RTL coding, FPGA, DFT, lower power, hierarchical front/backend design flows/utilities.
Cadence: NC Verilog/Genus/CCD/Verplex-LEC&CLP/ Encounter/Platform .
Synopsys: DC/DCG/Siloti/ Formality/Prime-Time/Power Compiler /VCS /HSpice.
Xilinx: ISE -Virtex/Spartan -6 Series, Vivado-Virtex-7.
Incentia: Designcraft ( Scan Insertion ).
Mentor: BistArchitect /Tessent ( TK/ATPG ).
Novas Verdi: Netlist/Waverform Tracker.
Dorado: Tweaker ( Timing ECO ).
UMC/Faraday: ASICDK/ Flre/Ferc/Fpgc/Ftip/Ftlutil/Fipcon .
IBM: ASOK/Net-list Processing/EinsTimer/Floor-Planning/Verification.
FTC: Design Kits/flre/ferc/ftcv/ftip/fipcon/ftl2ver. Related Software:
C, C++, Tcl/Tk, Perl, JAVA, Matlab, Assembly Language
8051&8016 Emulator, Metlab, LabVIEW, SPICE and Unix/Linux EXPERIENCE
Mar.’04 –Present Sr. ASIC technical Manager. Faraday Tech.Corp. Hsinchu Sci. Park, Taiwan
Led the implementation team providing turnkey key solutions and technical consultants for wireless backhaul SoC projects with high performance Serdes, PCIE, ADC/DAC key IPs embedded and reaching the 1st cut sample work on flip-chip products.
Main technical leader for LDPPM automobile head-up display project, conquer the issues on data skewing, on-chip variation, jitter analysis, over constrains on multi-V IO and timing closure to meet the tape-out criteria at RTM phase .
Main technical leader for DSC SoC project with ultra-low power, embedded high performance mix-mode IPs, MIPI D/M-PHY, DDR4, HDMI, USB3.0, H264, H265, partition power planning upon the sub systems for CEVA-XM4, Hs38, Cortex-A9, processors in WLCSP met the on-time delivery with In&Out criteria .
Joint Taskforces in optimization in embedded high performance CPU (single, dual and quad cores) for power and physical aware design architecture, bus bandwidth, performance enhancement test chips, on flow RCP/RTL and LPE/Net-list, hitting the final goal with silicon proven for ASIC projects .
Post Tape-Out services on patterns development, simulation, validation under function and test modes for yield enhancement, fulfilling the plan targets from clients, in various applications as Pen Drive-USB2/3.0, GPS baseband, Bar-Code, SATA PCIEG, eMMC, ONFi and customized peripheral devices.
1st FTC CASHCOW Awards owner for the most high-volume ASIC consumer electronic products.
Mar.’02–Feb.’04 Sr. ASIC Design Engineer. Leadtek Research Inc. New Taipei City. Taiwan
Algorithms ( DCT, FFT, H264 & H265 ) develop from RTL Verilog coding into FPGA and successful demonstrate on real systems of surveillance, head mounted display and Image Phone Sets.
Prototyping transferring FPGA for video connector : 720x480/YUV4:2:2, CCIR656
(8Bits data bus + clock/27MHz /9pins) vs. CCIR601 ( V/H-sync 13.5MHz/19pins ), successfully demonstrate programing ratios in trade fair booth .
Testing cost reduction with customized parallel DFT include the MBIST, IPs, x4 ports USB, LVDSRX/TX on production load board s.
Main designer of image phone chipset, and pixel scaling unit for head mounted display.
Oct.’00 –Feb.’02 ASIC Design Engineer. Leica Geo-systems Inc. Torrance CA. USA
Designed multiple channels, dual frequency, high precision GPS receiver and test- benched with satellite simulator for logical verification on ASIC/FPGA.
Designed and developed RTL for DSP modules and validated programmable points double-precision complex FFT on IBM SA27E.
Designed the bus simulator to verify data transfer through DMA controller with IBM UART750, USB, I2C, FIFO and evaluated system I/O capabilities.
Designed dual frequency satellite simulator and customized User Time Clock for multiple peripheral devices to alleviate the meta-state/BIST
Converted RTL modules from ASIC to FPGA for datum collection and logic verification on Xilinx’s Virtex –Series.
Analyzed static timing and area on back-end net-list processing and finalized ASIC development – System Clock from 43.5MHz to 200MHz.
Designed efficient digital code conversion technique to solve the limitation on FPGA for ASCII coded string to binary 32-bits converter. Sep. ’98 –Fall ’00 Research Assistant Dep. of Electrical Engineering in UTSA Antonio. USA
Implementation for high performance Pipeline CPU developing into Xilinx FPGA.
Exploring History Correlation for Various Dynamic Branch Prediction Schemes Algorithms were simulated in UNIX SPARC and datum obtained by shade version 5.25 analyzer.
Intern on practical training SUN Micro System Core development Center in RTL coding for branch prediction unit.
Developed the Branch Prediction Unit on Xilinx’s FPGA platform and tested with benchmark program from Stanford Baby Benchmark Suite.
Designed for test on IBM C5S904_OPB_BRG Macro with multiple clock rates and 16/64 bytes FIFO. TA at Logic design and Computer arithmetic.
Designed automatic detection of tumors ASIC in breast cancer infrared images coding in Matlab and converted to Verilog HDL with UTMC.
Master of Science in Electrical Engineering
University of Texas at San Antonio, Texas, USA GPA 3.55 out of 4.0 Bachelor of Science in Industrial Electrical Engineering
Chung Cheng Institute of Technology, Taiwan. R.O.C. GPA 3.52 out of 4.0 HONOR/AWARDS
Received Department of Defense (DOD) Scholarship for being one of the Top graduate students.
Received the Outstanding Engineer Award from the NAVY, R.O.C. PUBLICATION
Power Saving and Cost Reduction on ASIC Fast-Fourier-Transfer Processor Design In submitting IEEE 2002.
Master Thesis, University of Texas at San Antonio. Efficient Branch Prediction Techniques for High-Performance CPUs. 2000.
Caching Alias Branches in Small Temporal Vicinity. USA ICCA 1999. REFERENCE
Available upon request.