Design Electrical Engineering

**** ***** ***** ******

Santa Clara

CA, *****

C: 213-***-****

SAVINAYA RAJENDRA

ac4mzc@r.postjobfree.com

ac4mzc@r.postjobfree.com

https://www.linkedin.com/in/

savinaya-rajendra-77145a133

Technical Skills

Hardware Description languages: Verilog HDL

Programming Languages: Python, C++, C, Data Structures and Algorithms Tools: HSpice, Cadence Virtuoso, ModelSim, Pin tool, Cacti, MatLab, Simple Scalar, Synopsys Firmware skills: Embedded C, RTOS, ARM Architecture, Debugging GDB Internships

Trainee July 2015

Bharath Heavy Electricals Ltd (BHEL), Bengaluru, India Trained ON:

• Control Equipment Area

• Subassembly, Max DNA Systems

• Semiconductor and photovoltaics

• Traction system, excitation system, Generator Control In-plant Trainee June 2014-July 2014

Kaynes Technology, Mysuru, India

• Component Identification

• Electro Static Discharge

• Surface Mount Technology- PCB assembly, testing

Projects

Full Custom CPU Design Nov 2017

Physical Design Cadence Virtuoso

• Designed a 5-stage pipelined processor

• Optimized for Area and Power

• Python script used to generate the input vectors from the instruction in the fetch stage Performance Analysis of simple scalar OoO Processor Oct 2017 Simple Scalar, Cacti

• Study of the variation of power performance against the other component sizes

• Obtained configuration to deliver highest MIPS within the area, transistor count budget PTM FinFET DRAM Oct 2017

Physical Design Hpisce

• Designed 1 bit a FinFET DRAM in 7nm technology

• Python script was written to compare the number of Fins for different capacitance values

• MatLab used to obtain the comparison graph

Full Custom SRAM Design Sept 2017

Physical Design Cadence Virtuoso

• Designed a 1024-bit SRAM with sense amplifier, row decoder, column decoder, column multiplexer and registers

• Optimized for minimum area delay product

• Python scripting was used to translate the command file into vector file and functional verification was also done Silicon Wafer Processing May 2017 – July 2017

Solid State Integrated Circuit Fabrication

• Fabricated diode, resistors, capacitors, MOSFET on a 3 inch <1 0 0 > p type Silicon wafer in a clean room

• Process used- lithography, wet etching, diffusion, baking, plasma etching, metallization

• Electrically characterization of the devices

Neural Network June 2017

Physical Design Cadence Virtuoso

• Designed a circuit which emulates a neuron which was later connected to 15 neurons to form a network

• Optimized the design to obtain a minimum area and delay product which was got as 7042 e-12 * 820ps. Clocked at 1.2GHz Vehicle Security and Tracking System Jan 2016 – Jun 2016 Embedded Systems

• Developed a system using Raspberry Pi, GSM and GPS modules

• Python code was used for providing the functionality Education

Master of Science Electrical Engineering Digital VLSI Design Expected Graduation: July 2018 University of Southern California, Los Angeles, CA Relevant Course work: EE457-Computer System Organization, EE477L-MOS VLSI Circuit Design, EE504L-Solid State Processing and Integrated Circuit Laboratory, EE557-Computer System Architecture, EE577A-VLSI System Design, EE599-Introduction to Bioelectricity and Biomimetic electronics EE577B-VLSI System Design.

Bachelor of Engineering Electronics and Communication Engineering Sept 2012-Sept 2016 The National Institute of Engineering, Mysuru, India GPA: 4.0/4.0 Relevant course work: CMOS VLSI Circuits, Low Power VLSI Design, Computer System Organization, Digital Design using Verilog, Digital Electronic Circuits, Data Structures and Algorithms, Electronic Instrumentation, Microcontroller, Microprocessor, ARM Processor, Embedded Systems, Internet of Things.

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