SAI SHRAVAN EVANA

*** ***** ******** **, ****, Phone: 205-***-****

Los Angeles, CA 90012 Email: ac3566@r.postjobfree.com:ac3566@r.postjobfree.com

mailto:ac3566@r.postjobfree.com

SUMMARY

●Electrical and computer engineer with 6 years of work experience in the semiconductor industry.

●Core competencies include root cause analysis, VLSI IC design verification, SoC silicon validation, DFM and DFT methodology, project management and ATE high volume testing.

●Expertise in C, Python, Verilog, Unix, Spice, AutoCAD, JMP, LabVIEW and MATLAB.

●Excellent interpersonal and communication abilities and a wide range of technical skills.

●Exceptionally good at mentoring, managing, motivating, and training a productive team.

EDUCATION

The University of Alabama, Tuscaloosa

M.S. in Electrical & Computer Engineering GPA: 3.77/4 Aug 2011

Jawaharlal Nehru Technological University

B.Tech in Electronics & Communication Engineering GPA: 3.75/4 May 2009

WORK EXPERIENCE

●Product Test Engineer at Mellanox Technologies Oct 2016 – Mar 2018

Project leader for SiP (Silicon Photonics) PE group.

Coordinate new product development from initial design phase to full production release.

Designed and developed custom testing hardware and software for Production test and characterization.

Ensured high quality product deliveries to the customer by the means of failure analysis, data analysis and yield analysis/enhancement.

Coordinated with Design and Manufacturing teams to develop robust test solutions for mass production.

Interfaced with process groups to improve or resolve process/product interactions resulting in delays of materials release or yield/quality issues after release.

Actively involved with Marketing, and Applications Engineering for debug and customer problem solving.

Performed NPI Qualification and Reliability activities.

●DRAM Mobile/Module Test Engineer at Micron Technology Sep 2011 – Sep 2016

Contributed significantly in reducing the test cost/GB ratio by 14% and improving the yield by 2.8% on DDR4 (all DIMMs) modules.

Contributed significantly to overall yield improvement on LPDDR1/2 products by 6.3% and reduced the test cost/GB ratio by 11%.

Implemented DFT features, developed new test methodologies & ran simulations for validation on silicon.

Analyzed package level characterization data and developed necessary patterns for functional and parametric stress testing of packaged parts at production time on ATE.

Created programs for functional and parametric testing of several different DDR3/DDR4 module classes, including RDIMM, SODIMM, CDIMM, & NVDIMM.

Solved several challenging test-time problems by developing novel test methodologies that included the creation of unique functional test patterns, modulation of stress voltage and temperature, array compression testing optimization, etc.

Successful in deploying proper test coverage by leveraging test equipment including Oscilloscopes and Logic Analyzers to analyze and debug customer RMAs and other production failures.

Lead First Silicon NPI module test program creation, stress patterns, repair/ECC coverage, etc. to have the test flow ready in time-constrained situations.

Generated the Statistical Process Control charts to periodically monitor the test yields.

Developed scripts to automate post-test data spooling and real-time production test monitoring.

Collaborated with several groups, including Marketing, Product Planning, Assembly, Quality and SLT, on NPI modules to ensure seamless movement from initial build to production test. Optimized time to market.

RESEARCH EXPERIENCE

●Design and Self-Calibration scheme for RF Circuits using MEMS in 3D Packages

Designed a low noise amplifier (LNA) operating at 5GHz with only capacitive and inductive matching elements and a maximum operating gain of 8.9db

Designed a novel BIST circuit with power sensors in BiCMOS process to localize the parametric faults on the LNA

Designed a novel tuning circuit based on inductive switching technique using MEMS switches to automatically calibrate the parameters of the LNA

RESEARCH PROJECTS

●3D Copper Based TSV for 60GHz Applications

●Analysis of CNT Based 3D TSV for Emerging RF Applications

●RF Circuit Testing and Calibration using MEMS

●High Frequency Modeling and Measurement Techniques for On-Chip Planar Inductors

RELEVANT COURSES

●Brand and Product Management

●Introduction to Marketing

●Introduction to Operations Management

●Mixed Signal Circuit Design

●Microsystems Packaging

●VLSI Design

●RFIC: Design and Analysis

●Solid State Devices

●Digital Signal Processing

●Sensor Networks

COMPUTER AND EDA TOOLS

●Software Languages

C, C++, Python, Unix & SQL

●Hardware Languages

VHDL & Verilog

●Automatic Test Equipment

Advantest T5585/86

●Simulation Tools

MATLAB, P Spice, H Spice, Electric, Advanced Design System, PowerSI, LabVIEW & CST Studio

●Data Analysis Tools

JMP, Excel, DPlot

●CAD Tools

Cadence Virtuoso Schematic Editor, Xilinx ISE & OrCAD

●Hardware Instruments

Working knowledge of high-end Oscilloscopes, Logic Analyzers, Signal Generators, etc.

●Other

Microsoft Office Suite (Word, Excel, PowerPoint, etc.), Visual Studio 10, dataPOWER

EXTRA-CURRICULAR ACTIVITIES

●Dance Instructor, Latin ballroom dancing

●Vlogger/YouTuber, Avid fragrance collector and reviewer

REFERENCES: Available upon request

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