| Resume alert | Resumes 91 - 100 of 194 |
Design Electrical Engineering
Los Angeles, CA
... Circuit Design (EE477) Project Experience DDR3 Controller Design (Verilog, NCSim, DC Compiler, Prime Time, Cadence Encounter) November 2016 Designed a DDR3 controller in Verilog RTL supporting Scalar, Block, Atomic Read/Write and refresh operations; ... - 2017 Feb 10
... Circuit Design (EE477) Project Experience DDR3 Controller Design (Verilog, NCSim, DC Compiler, Prime Time, Cadence Encounter) November 2016 Designed a DDR3 controller in Verilog RTL supporting Scalar, Block, Atomic Read/Write and refresh operations; ... - 2017 Feb 10
Design Software Engineer
Los Angeles, CA
... Ananthapur, India GPA: 3.70/4.0 B.Tech, Electronics & Communication Engineering, 2009-2013 PROGRAMMING/TECHNICAL SKILL SET: CAD tools : Cadence Virtuoso, HSPICE, MATLAB Simulink Languages : C, VHDL, Verilog HDL, SQL, PL/SQL and UNIX Scripting. ... - 2017 Feb 01
... Ananthapur, India GPA: 3.70/4.0 B.Tech, Electronics & Communication Engineering, 2009-2013 PROGRAMMING/TECHNICAL SKILL SET: CAD tools : Cadence Virtuoso, HSPICE, MATLAB Simulink Languages : C, VHDL, Verilog HDL, SQL, PL/SQL and UNIX Scripting. ... - 2017 Feb 01
Electrical Engineer Design & Test
Irvine, CA
... Strong knowledge on RTL, FPGA, HDL/VHDL and Verilog. Instruments: Agilent 8960 Series 10 Wireless Communication Test Set (GSM, GPRS, EDGE, WCDMA, FASTSW, HSDPA, RF Spectrum). Agilent HP 3070 ICT Tester & Teradyne Spectrum 8000. HP 8510c Network ... - 2017 Feb 01
... Strong knowledge on RTL, FPGA, HDL/VHDL and Verilog. Instruments: Agilent 8960 Series 10 Wireless Communication Test Set (GSM, GPRS, EDGE, WCDMA, FASTSW, HSDPA, RF Spectrum). Agilent HP 3070 ICT Tester & Teradyne Spectrum 8000. HP 8510c Network ... - 2017 Feb 01
Project Design
Tustin, CA
... oTop Level Simulation Test & Debug, Verilog (4 years), C programming (4 years) and RTL oFPGA (4 years), ARM 7, 8, 9 and 10. Technical Skills Programming: VHDL / Verilog HDL, PERL, System C, Vera, C, C++, keil C, Fortran, Assembly language. ... - 2016 Nov 30
... oTop Level Simulation Test & Debug, Verilog (4 years), C programming (4 years) and RTL oFPGA (4 years), ARM 7, 8, 9 and 10. Technical Skills Programming: VHDL / Verilog HDL, PERL, System C, Vera, C, C++, keil C, Fortran, Assembly language. ... - 2016 Nov 30
Hardware Design Engineer
Los Angeles, CA
... India Aug’14 Bachelors of Technology in Electronics and Communication Engineering GPA: 3.8/4 Technical Skills: Languages : Verilog, VHDL, System Verilog, Perl, Bash, C++, Python, Tcl, JAVA, Assembly Language (MIPS, 8086) Tools : PinSesc, Encounter, ... - 2016 Nov 14
... India Aug’14 Bachelors of Technology in Electronics and Communication Engineering GPA: 3.8/4 Technical Skills: Languages : Verilog, VHDL, System Verilog, Perl, Bash, C++, Python, Tcl, JAVA, Assembly Language (MIPS, 8086) Tools : PinSesc, Encounter, ... - 2016 Nov 14
Software Engineer
Huntington Beach, CA, 92648
... Development Enterprise-class Web Applications Skills: Programming Language: C\C++, C#, Java, JavaScript, HTML/CSS, SQL, Verilog, Assembly Development tool: WebStorm, Git, Visual Studio, AngularJS, wow.js, Asp.net UX/UI Design: A/B Testing, 3D max, ... - 2016 Nov 11
... Development Enterprise-class Web Applications Skills: Programming Language: C\C++, C#, Java, JavaScript, HTML/CSS, SQL, Verilog, Assembly Development tool: WebStorm, Git, Visual Studio, AngularJS, wow.js, Asp.net UX/UI Design: A/B Testing, 3D max, ... - 2016 Nov 11
Manager Systems Administrator
Los Angeles, CA
... Software installation (Verilog, Synopsys, video conference, CAD tool updates,etc.). UNIX System software upgrades. Bourne Shell programming. C Shell programming. UNIX System maintenance. UNIX peripheral configuration and maintenance. SOLARIS 2.51 ... - 2016 Nov 01
... Software installation (Verilog, Synopsys, video conference, CAD tool updates,etc.). UNIX System software upgrades. Bourne Shell programming. C Shell programming. UNIX System maintenance. UNIX peripheral configuration and maintenance. SOLARIS 2.51 ... - 2016 Nov 01
Technical Support Software Developer
Los Angeles, CA
Kevin Mitton ***** ******* **** #**** Woodland Hills, CA 91367 Tel: 909-***-**** Email: acvxsy@r.postjobfree.com T echnical Skills ● Proficient knowledge and experience using C, C++ for school projects (5 years) ● Beginner knowledge using Verilog ... - 2016 Jul 29
Kevin Mitton ***** ******* **** #**** Woodland Hills, CA 91367 Tel: 909-***-**** Email: acvxsy@r.postjobfree.com T echnical Skills ● Proficient knowledge and experience using C, C++ for school projects (5 years) ● Beginner knowledge using Verilog ... - 2016 Jul 29
Engineer Computer Science
Irvine, CA
... • Created a Python library to parse System Verilog (SV) netlists to analyze and modify their structure. • Created a tool to analyze analog designs and autogenerate SV models which describe behivor. • Desiging verification and design methodoligies by ... - 2016 Jul 12
... • Created a Python library to parse System Verilog (SV) netlists to analyze and modify their structure. • Created a tool to analyze analog designs and autogenerate SV models which describe behivor. • Desiging verification and design methodoligies by ... - 2016 Jul 12
Design Data
Los Angeles, CA
... Digital Computers (EE-658) Integrated Memory Devices and Technology (EE- 599) Technical skills: Programming Languages: Verilog, Perl, VHDL, TCL, System Verilog, MATLAB, C Packages/Tools: Cadence Tools(Virtuoso,Spectre), Xilinx ISE Design Suite, ... - 2016 Jul 08
... Digital Computers (EE-658) Integrated Memory Devices and Technology (EE- 599) Technical skills: Programming Languages: Verilog, Perl, VHDL, TCL, System Verilog, MATLAB, C Packages/Tools: Cadence Tools(Virtuoso,Spectre), Xilinx ISE Design Suite, ... - 2016 Jul 08