Verification Engineer

SRINIVAS

Mobile : +91-953*******

Email: ******************@*****.***

Professinal Summary

Having around 2 years of professional experience in Semiconductor Industry, Involved in ASIC Verification projects and EDA Tools like Questa sim,Quartus and Mode sim.Functional Coverage and Code Coverages.

Experience and knowledge in UNIX,Linux,Synopsis Tools,Verilog and C.

Experience in ARM/AMBA Proessor system.

Experience in ASIC Verification,Develop test plans.

Experience in Functional Coverage and Code coverage.

Good understanding of the ASIC and FPGA design flow.

Experience in writing Test Benches in System Verilog and methodologies like UVM,OVM.

Very good knowledge in verification methodologies especially UVM.

Experience in using industry standard EDA tools for the front-end design and verification.

Educational Profile

Completed Bachelor of Technology from Sri Chundi Ranganayakulun Engineering & Technology(A.P).

Professinal Experience

Worked as ASIC Verification engineer for CVC Pvt Ltd,Bangalore since April 2015 to Present.

I did internship at CVC Pvt Ltd,Bangalore from October 2014 to March 2015.

Roles & Responsibilites

Developed test plans.

Verified the function RTL design.

Implimented the ASIC Verification processes.

Collabarated with the ASIC team,system group,architects and deisgn team.

Verified ASIC design and cycles from architecture and creating of ASIC test.

VLSI Domine Skills

HDL : Verilog

HVL : SystemVeriliog

Verification Methodologies : Coverage Driven Verification

Assertioin Based Verification.

TB Methodologies : UVM,OVM.

Bus Protocol : AMBA APB,AHB,SPI.

EDA Tools : Questa sim,Quartus and Mode sim.

Domain : ASIC/FPGA Design Flow,Digital Design.

Knowledge : RTL Coding,FSM based design,Simulation,

Code Coverage,Functional Coverage,Synthesis.

Scripting Language : Perl,Shell,Makefile.

Employment Experience

Project#

Title :AHB To SPI Controller

Role :Verification.

EDA Tool :Quasta Sim.

Resposbilities:

Understanding the specification

Verification plan devolepment in Questasim readable format.

Developed class based verification Environment for AHB to SPI controller.

Developed Driver functionality for Master and Slave

Developed Monitor,Scoreboard and Sequencer.

Developed Sequence-item,Constraint,Virtual Sequences and Test cases

Developed Verification Plan and Testcases,Functional Coverage Check.

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