verilog,system verilog, vlsi cad

ANUPAM NANDY mob-963-***-****

*****-********@*****.***

#***,*** *****,*** ******, kadugodi, Belathur, Bangalore- 560067, India

EDUCATION

PES Instititute of Technology, Bangalore, India Eq. GPA: 7.95

BE, Electronics and Communication Engineering, Aug 2012 – June2016

CBSE-

10 standard-89.6%

12 standard-74.5%

ACADEMIC PROJECTS

Home Security System using smart lock, Hardware Engineering Jan-May 2016

Prototype design of the smart lock was developed using arm7 kit,stepper motor,keypad and GSM module.

Also built a password generator app which generates a password for every visitor requesting to open the door.

Used embedded C for coding.

Modified carry select adder design, Hardware Engeering Aug – Dec 2014

Created a design to give lesser power, area and delay results of about 50% reduction and implementation using verilog.

Worked on the cadence tool and mentor graphics tool(digital section) to obtain the results.

Verification of UART, Hardware verification April 2016 -June 2016

Created an environment around the UART and observed the functional coverage report and code coverage reports.

Used incisive metrics centre to obtain the coverage reports. Tried out as many test cases as possible using both directed test cases and random test cases. Used many constraints to cover all the corner cases.

Used maximum number of assertions to identify bugs in the design

Verification and design of AHB2APB bridge,Hardware verification and design April 2016 -June2016

Used the amba protocol for designing the bridge using double synchronizers for the APB clock .

Used the cadence VIP s for the ahb and APB master and slaves.

Build the bridge design using finite state machines and coded it in Verilog

Used incisive metrics centre to obtain the coverage reports. Tried out as many test cases as possible using both directed test cases and random test cases. Used many constraints to cover all the corner cases.

Used maximum number of assertions to identify bugs in the design.

INTERNSHIPS AND RELATED COURSE WORK

CADENCE DESIGN SYSTEMS(VERIFICATION TRAINEE) jan 2016 -june2016-Did labs on system verilog topics such as data types, classes, interfaces, assertions, clocking blocks, virtual interfaces, randomization, inheritance, scoreboards, functional coverage, etc using incisive tool and incisive Metrics Center. Later did a project on verification on UART.Also did a project on ahb2APB bridge deign and verification.

Digital logic design – combinational and sequential circuit optimization, timing parameters, glitches and hazards, memories, fsm models.

Course Name – Blended learning programme

VLSI – cmos circuits, memories, fsm, logic gates,combinational and sequential circuits .

Course Name – Computational Structures

TECHNICAL SKILLS

Operating Systems: Linux, Windows 98/2008/07/XP

Programming Languages: C, Verilog, System Verilog

Software and protocols: Xilinx, Incisive, Incisive Metrics Center, mentor graphics, Questa Sim,dev C++, UART,AMBA.

HONORS

Distinction certificates

Digital logic design course certificate-560674051

Certificate of participation in TEXAS ANALOG MAKER contest

Computational Structures course by MIT

International Math Olympiad National Talent Certificates 2007,11.

Training certificate from cadence from Jan-June 2016.

EXTRA-CURRICULAR

Workshop on ethical hacking by iit Bhubaneshwar.

Attended the IET Pinkerton lecture on the Internet of Everything by Dr. Robert Perry

Smart tech workshop on September 2015-09-24 and 25

Course on python by internshala.

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