| Resume alert | Resumes 61 - 70 of 107 |
Test Cases Professional Experience
Orange, CA
... Tools: Eclipse, Google Map, Developer tools, HP tools, Chef GUI Text Editors: Notepad++, Sublime Software: Matlab, Vhdl, Verilog, Keil Other tools: Jenkins, Hudson, Github, Git, Svn, Aws PROFESSIONAL EXPERIENCE Splan.inc, Fremont, CA April 2015 – ... - 2016 Mar 01
... Tools: Eclipse, Google Map, Developer tools, HP tools, Chef GUI Text Editors: Notepad++, Sublime Software: Matlab, Vhdl, Verilog, Keil Other tools: Jenkins, Hudson, Github, Git, Svn, Aws PROFESSIONAL EXPERIENCE Splan.inc, Fremont, CA April 2015 – ... - 2016 Mar 01
Engineer Electrical Engineering
Irvine, CA
... Line Diagrams using SKM Power Tools Skills: Good understanding of SKM Power Tools, PowerWorld, ETAP and LabVIEW C++ programming, Verilog and assembly language MATLAB Good understanding of Unix and Linux OS PSPICE simulations with Digital and Analog ... - 2015 Dec 28
... Line Diagrams using SKM Power Tools Skills: Good understanding of SKM Power Tools, PowerWorld, ETAP and LabVIEW C++ programming, Verilog and assembly language MATLAB Good understanding of Unix and Linux OS PSPICE simulations with Digital and Analog ... - 2015 Dec 28
Manager Engineer
Irvine, CA
... * Awards/ Publications: 1 issued and 2 pending patents in iStor Networks SKILLS: FPGA Design: - Altera, Xilinx VHDL & Verilog for logic entry: - ModelTech, Synplicity, MaxPlus Firmware Design: - C++, C# ASIC Design - LSI Logic Tools, Toshiba ... - 2015 Dec 11
... * Awards/ Publications: 1 issued and 2 pending patents in iStor Networks SKILLS: FPGA Design: - Altera, Xilinx VHDL & Verilog for logic entry: - ModelTech, Synplicity, MaxPlus Firmware Design: - C++, C# ASIC Design - LSI Logic Tools, Toshiba ... - 2015 Dec 11
Project Design
Orange, CA
... Technical strengths: Proficient with RTL design using Verilog HDL and System Level Design as well as System Verilog and Open Verification Methodology (OVM). FPGA-based design on a Network on Chip communication channel research project. Good ... - 2015 Dec 08
... Technical strengths: Proficient with RTL design using Verilog HDL and System Level Design as well as System Verilog and Open Verification Methodology (OVM). FPGA-based design on a Network on Chip communication channel research project. Good ... - 2015 Dec 08
Engineer Office
Long Beach, CA
... Internet Protocols: TCP/IP, IP, ARP, ICMP, TCP AND UDP Software Tools: • Operating Tools: Wire shark, Cisco packet tracer, GNS3, MATLAB, Xilinx v8.4 (VHDL, Verilog), Kiel v3, Solid Edge v 21, Pspice, OptiPerformer, OptiSystem, LTspice, or CAD, MS ... - 2015 Nov 01
... Internet Protocols: TCP/IP, IP, ARP, ICMP, TCP AND UDP Software Tools: • Operating Tools: Wire shark, Cisco packet tracer, GNS3, MATLAB, Xilinx v8.4 (VHDL, Verilog), Kiel v3, Solid Edge v 21, Pspice, OptiPerformer, OptiSystem, LTspice, or CAD, MS ... - 2015 Nov 01
Design Engineering
La Habra, CA
... EDA Tool -- Mentor Graphics PCB Schematic Capture/Simulation, PADs PCB Layout Viewer, OrCad PCB Schematic Capture, Cadence Verilog tools, Viewlogic Powerview, Altera/Xilinx FPGA HDL/Schematic, Synplicity, ... Profession Experiences ILY Enterprise, ... - 2015 May 15
... EDA Tool -- Mentor Graphics PCB Schematic Capture/Simulation, PADs PCB Layout Viewer, OrCad PCB Schematic Capture, Cadence Verilog tools, Viewlogic Powerview, Altera/Xilinx FPGA HDL/Schematic, Synplicity, ... Profession Experiences ILY Enterprise, ... - 2015 May 15
Customer Service Engineer
Paramount, CA
... Worked with managing ink printer and other printing applications SKILLS Language: Bilingual, Fluent Spanish (verbal and written) Computer: C++, Java, Xilinx, Verilog, MatLab, MS Office-Word, Excel, PowerPoint, Pagemaker, Photoshop, Illustrator, ... - 2014 Aug 26
... Worked with managing ink printer and other printing applications SKILLS Language: Bilingual, Fluent Spanish (verbal and written) Computer: C++, Java, Xilinx, Verilog, MatLab, MS Office-Word, Excel, PowerPoint, Pagemaker, Photoshop, Illustrator, ... - 2014 Aug 26
Design Engineering
Irvine, CA
... Software Skills: Languages: C/C++, HTML, Assembly (8088 and AVR ATMega8), Verilog(basic) Packages: Hspice, Cadence, OrCAD, Mentor Graphics, Eagle PCB, MultiSIM, Microwind, LABVIEW, MATLAB Publication: “Fully Integrated, Highly Linear, Wideband Low ... - 2014 May 22
... Software Skills: Languages: C/C++, HTML, Assembly (8088 and AVR ATMega8), Verilog(basic) Packages: Hspice, Cadence, OrCAD, Mentor Graphics, Eagle PCB, MultiSIM, Microwind, LABVIEW, MATLAB Publication: “Fully Integrated, Highly Linear, Wideband Low ... - 2014 May 22
Medical Device Quality Assurance
Los Angeles, CA
... GMP ● CAPA ● ISO 13485 ● ISO 14971 ● 21 CFR 820 Skills Solidworks ● Auto CAD ● C/C++ ● Matlab and Simulink ● 8086/51 assembly ● Verilog Biomaterials and Tissue Engineering ● English and Mandarin Chinese Honors National Scholarship for Encouragement ... - 2014 Mar 26
... GMP ● CAPA ● ISO 13485 ● ISO 14971 ● 21 CFR 820 Skills Solidworks ● Auto CAD ● C/C++ ● Matlab and Simulink ● 8086/51 assembly ● Verilog Biomaterials and Tissue Engineering ● English and Mandarin Chinese Honors National Scholarship for Encouragement ... - 2014 Mar 26
Engineer Design
Irvine, CA
... Design and Verification Engineer (Implanted Receiver, Decoder, Neurons Stimulation Controller Digital Architecture Design and Verification and achieving 40% performance improvement with proposed new embedded-mode architecture RTL in Verilog and VHDL ... - 2013 Dec 28
... Design and Verification Engineer (Implanted Receiver, Decoder, Neurons Stimulation Controller Digital Architecture Design and Verification and achieving 40% performance improvement with proposed new embedded-mode architecture RTL in Verilog and VHDL ... - 2013 Dec 28