Project Design

Curriculum Vitae

Mario A. Hernández Zárate E-Mail: *****.******@*****.***

**** *. *** **** **. Orange, Ca 92869 Mobile: 714-***-****

Objective:

To obtain employment as an Electronics/Hardware Engineer in a dynamic and creative research environment where I can enhance my knowledge and put in practice everything I have learned especially in hardware design.

Technical strengths:

Proficient with RTL design using Verilog HDL and System Level Design as well as System Verilog and Open Verification Methodology (OVM).

FPGA-based design on a Network on Chip communication channel research project.

Good understanding of Computer Architecture, Digital Integrated Circuit Designs, DSP architecture.

Experience in using various CAD tools such as Cadence, Mentor Graphics, VCS, and Xilinx ISE.

Academic Background:

Completed Master’s Degree from the University of Edinburgh, UK in the year 2009 with System Level Integrator as the major subject, with 59% coursework and 60% on the project.

Obtained Bachelor of Electronics Engineering with 93.3 %, First Class “Honors” from the Technological Institute of Orizaba, Mexico in the fall of 2001 Department of Electronics with Instrumentation Engineering as the major subject.

Skills (Tools and Languages):

FPGA Tools: Xilinx ISE, Modelsim XE, VCS

Programming: Verilog, System Verilog, C,UML, OVM

Assembler: Microchip PIC16F84, Arduino

Relevant Project Experience:

Intel Labs, Pondicherry architecture verification and rtl design, Guadalajara, October 2010 to March 2012.

Project Description:

On this project I was able to lead my team to have a successful outcome. Basically it was achieved by listening their needs and attacking the issues on daily scrum meetings. This project consists of a NoC used to connect two cores and two accelerators, using the MESI protocol to handle shared memory. The coherency system includes 4 Pondicherry interfaces along with a memory port and a register interface. The master core is connected to the system using the front side bus later translated to a Pondicherry interface. Any device connected to these ports can issue transactions to memory and the coherency controller would issue snoops to the corresponding connected devices.

A test-bench was written in System Verilog using the OVM library (to speed up construction and deployment) in order to verify the coherency controller and crossbar. This test-bench consists of a set of drivers that could issue randomly generated transactions to the DUT and a set of responders capable of replying consistently to the following snoop requests. The register interface as well as the memory interface was connected to their respective responders (drivers).

Checkers and scoreboards were implemented to validate the DUT's correctness. And every transaction that occurred during a simulation was logged for future processing. Functional coverage monitoring modules were added to compute coverage.

In order to check the coherence on the main memory agent and the caching agents, a set of perl scripts were used to compare the logged data and see if there were any coherence errors. This testbench enabled us to reach full functional coverage and a very high (> 90%) code coverage in average. In addition to this, most of the monitors and checkers were reused for full-chip simulation embedded in a SystemC testbench.

Later on, since the chip was not physically available, some modules were done to be prepared when the chip arrives. These modules were designed at RTL level using verilog to implement the i2c protocol used to transmit and receive data from the chip. The position I held on this particular project was as a tech lead, holding quick daily meetings with the team to address any particular issue related to the hardware design team direction or the decisions to be made within our verification plan team.

SVE Group, Cloverview, Tangier, Anniedale Validation, Guadalajara, May 2012 to March 2014

Project Description:

On this project the work is done on the post silicon area, working on the validation of the SoC which is called Anniedale, previous versions were Anniedale, Clover View (CLV) and Clover View Plus (CLVP). The purpose of this project is to run test with concurrency to stress the chip and find any possible bug, to find out if there is a problem with the hardware or the software. After finding bugs they are posted on presightings or sightings so the other teams from India or US can reproduce this issue so that later all the teams can sit and discuss and come to a general agreement to decide if it can be fixed with a register on the hardware or make a workaround to fix issues without compromising the silicon. If the issue can be solved by these workarounds, then the hardware architects have to verify the chip on RTL design and verify it again so they can solve it and come out with another chip. This new versions called A0, B0 and even C0 till the product is ready without any bugs and is ready to go to market. The main role here is to find bugs in the area of USB3. Nevertheless when the USB is run with other modules such as graphics there might be a USB bug; however isolation must be done step by step until the root cause is found. Then one can be clear where the bug is. By running these tests I have been able to tell the developers very quickly where the problem is located so they can easily find the root cause. By interacting and coordinating the firmware team as well as developers it has been possible to solve all these issues in a very short period of time by email or telephone. Mostly all these issues are solved very quickly when we gather in a single physical location, people from different countries joining together as team and creating an excellent work environment.

Center for Computing Research, National Polytechnic Institute, Mexico City, May 2014 to “Present”

Project Description:

Currently developing the modules for a Superscalar processor, this processor executes 4 instructions per clock. The architecture is based on the MIPSR10000 and Alpha processors. There are 32 logical registers which are translated into 128 physical registers on the renaming stage to avoid any dependencies. Those instructions are then dispatched to the issue logic. On this module there is a wake up logic that determines which instructions can be freed for execution. This is the place where the instructions are executed out of order. Regarding the Branch predictor it is based on dynamic history, so it can have a better accuracy than static predictors. The modules currently being developed are the Branch Predictor, Allocation-Rename, Mapper-Dispatch and Reorder Buffer.

Internship Experience: National Polytechnic Institute, October 2009 to November 2010

Project Description:

Working on a superscalar processor, on this particular project, I was working on the RTL architecture implementation, making sure that the free register list, as well as a dual port ram gets the proper registers renamed and gets the proper output to the next stage. This contains 32 logical registers with 128 physical registers, four instructions per clock are permitted and from there the renaming logic is implemented. The free register list comes from the ROB (re-order buffer) but for this particular patent, the registers are simulated and introduced to the free register list. Exploration on design of the ROB and instructions tale was explored. From the area of renaming professors decided to do a patent so I am collaborating with them to do some slightly modifications to present according to the patent requirements.

Thesis Experience: Edinburgh University, NoC communication, using virtual channels, 2008 - 2009

Project Description:

Working on a NoC architecture, designing and implementing an architecture with Verilog to establish communication between the nodes on an Spidergon architecture, using the local link protocol and the implementation of virtual channels.

Academic Contests:

Intelligent Heater, at The Technological Institute of Orizaba, Veracruz, 2nd place, June, 2001.

This device was created using PLD and then transferred to a microprocessor (PIC). The main objective was to control the gas consumption on the heater by opening or closing it, according to the set time.

Regional System Positioning at the Technological Institute of Orizaba, Veracruz, participant, June, 2001.

Objective was to see the location of a vehicle by triangulating the signal.

Electronic Babysitter at The Technological Institute of Orizaba, Veracruz, participant, May, 2000.

This cradle was created with the addition of sensors to monitor the basic signals of a baby, to let the parents know if there was any problem.

Mathematics contest at the ITESM (Bachelor level), participant, and Physical contest at the CBTis (High School Level), 1st place, History contest, 1st pace, in November, 1998, June, 1996, January, 1994, respectively.

Awards & Achievements:

Awarded Scholarship to study abroad while doing a Master’s Degree.

Awarded Scholarship to study the bachelor course.

Achieved an outstanding academic record and given a Certificate of Merit from The Technological Institute of Orizaba, Veracruz for graduated at the top of my class.

International Examinations, community participation, and other interests:

TOEFL: 500 points, IETLS: Writing 7, Speaking 7, Listening 7, Reading 6.

IET and IEEE member since the year 2007.

Mentored undergraduate students in Digital Electronics, Physics and Mathematics, at The Technological Institute of Orizaba.

Other Interests:

Helping my community by starting a group connection between US and Mexico so Americans could do social service to help rural areas.

Swimming, Running, photography, Listening to music and playing the Piano, Learning languages (German and Japanese), Climbing Mountains leading a group, (up to 5,000 meters = 16,404 feet)

Helping Kids from my community, creating a foundation “Mama Gallina”.

Creating gadgets as well as doing an Electric Car from the ground.

Declaration:

All the above particulars are true and correct to the best of my knowledge and understanding.

Mario Arcadio Hernández Zárate, November, 2015

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