| Resume alert | Resumes 51 - 60 of 107 |
FPGA / ASIC Design Engineer
Fullerton, CA
Stephen Cole **** ********** ***, *********, ** *2835 Email: aczhiq@r.postjobfree.com Relevant Qualifications: ASIC / FPGA Design Engineer with over 15 years’ experience of design, implementation, simulation and co-verification of Verilog and VHDL ... - 2017 Mar 25
Stephen Cole **** ********** ***, *********, ** *2835 Email: aczhiq@r.postjobfree.com Relevant Qualifications: ASIC / FPGA Design Engineer with over 15 years’ experience of design, implementation, simulation and co-verification of Verilog and VHDL ... - 2017 Mar 25
Design State University
Fullerton, CA
... Embedded Systems field where my technical and analytical skills will be utilized to the maximum advantage of the organization and have 5 years of academic experience in these field with various languages knowledge like Verilog, System C and Python. ... - 2017 Mar 16
... Embedded Systems field where my technical and analytical skills will be utilized to the maximum advantage of the organization and have 5 years of academic experience in these field with various languages knowledge like Verilog, System C and Python. ... - 2017 Mar 16
Matlab, PSpice, hardware, circuit design, gate level logic design
Long Beach, CA
... & Networks, Microprocessor & Interfacing, Microcontroller & Interfacing Technical Skills Programming Languages: VHDL, Verilog, System Verilog, C, C++, Python, Matlab, LabVIEW Simulators: Microwind, DSCH, Xilinx ISE, Xilinx Vivado, Keil uVision, ... - 2017 Feb 11
... & Networks, Microprocessor & Interfacing, Microcontroller & Interfacing Technical Skills Programming Languages: VHDL, Verilog, System Verilog, C, C++, Python, Matlab, LabVIEW Simulators: Microwind, DSCH, Xilinx ISE, Xilinx Vivado, Keil uVision, ... - 2017 Feb 11
Electrical Engineer Design & Test
Irvine, CA
... Strong knowledge on RTL, FPGA, HDL/VHDL and Verilog. Instruments: Agilent 8960 Series 10 Wireless Communication Test Set (GSM, GPRS, EDGE, WCDMA, FASTSW, HSDPA, RF Spectrum). Agilent HP 3070 ICT Tester & Teradyne Spectrum 8000. HP 8510c Network ... - 2017 Feb 01
... Strong knowledge on RTL, FPGA, HDL/VHDL and Verilog. Instruments: Agilent 8960 Series 10 Wireless Communication Test Set (GSM, GPRS, EDGE, WCDMA, FASTSW, HSDPA, RF Spectrum). Agilent HP 3070 ICT Tester & Teradyne Spectrum 8000. HP 8510c Network ... - 2017 Feb 01
Project Design
Tustin, CA
... oTop Level Simulation Test & Debug, Verilog (4 years), C programming (4 years) and RTL oFPGA (4 years), ARM 7, 8, 9 and 10. Technical Skills Programming: VHDL / Verilog HDL, PERL, System C, Vera, C, C++, keil C, Fortran, Assembly language. ... - 2016 Nov 30
... oTop Level Simulation Test & Debug, Verilog (4 years), C programming (4 years) and RTL oFPGA (4 years), ARM 7, 8, 9 and 10. Technical Skills Programming: VHDL / Verilog HDL, PERL, System C, Vera, C, C++, keil C, Fortran, Assembly language. ... - 2016 Nov 30
Software Engineer
Huntington Beach, CA, 92648
... Development Enterprise-class Web Applications Skills: Programming Language: C\C++, C#, Java, JavaScript, HTML/CSS, SQL, Verilog, Assembly Development tool: WebStorm, Git, Visual Studio, AngularJS, wow.js, Asp.net UX/UI Design: A/B Testing, 3D max, ... - 2016 Nov 11
... Development Enterprise-class Web Applications Skills: Programming Language: C\C++, C#, Java, JavaScript, HTML/CSS, SQL, Verilog, Assembly Development tool: WebStorm, Git, Visual Studio, AngularJS, wow.js, Asp.net UX/UI Design: A/B Testing, 3D max, ... - 2016 Nov 11
Electrical Engineer Engineering
Rancho Santa Margarita, CA, 92688
... components using Visual Basic and TCL Worked with Xilinx FPGA tools (Vivado) to implement digital audio receiver/transmitter with Verilog Utilized hardware diagnostic tools to troubleshoot and repair malfunctions within an electronics lab Ran audio ... - 2016 Aug 29
... components using Visual Basic and TCL Worked with Xilinx FPGA tools (Vivado) to implement digital audio receiver/transmitter with Verilog Utilized hardware diagnostic tools to troubleshoot and repair malfunctions within an electronics lab Ran audio ... - 2016 Aug 29
Engineer Computer Science
Irvine, CA
... • Created a Python library to parse System Verilog (SV) netlists to analyze and modify their structure. • Created a tool to analyze analog designs and autogenerate SV models which describe behivor. • Desiging verification and design methodoligies by ... - 2016 Jul 12
... • Created a Python library to parse System Verilog (SV) netlists to analyze and modify their structure. • Created a tool to analyze analog designs and autogenerate SV models which describe behivor. • Desiging verification and design methodoligies by ... - 2016 Jul 12
Design Electrical Engineering
Fullerton, CA
... India GPA- 3.5 Technical Skills: Language: VHDL, Verilog, System Verilog, SystemC, Perl EDA Tools: Cadence (Virtuoso schematic/Layout editing), Microwind, Chip scope, Modelsim, Xilinx –vivado, Xilinx ISE, Synopsys, MATLAB, LT-Spice, DSCH, Hspice. ... - 2016 Jun 07
... India GPA- 3.5 Technical Skills: Language: VHDL, Verilog, System Verilog, SystemC, Perl EDA Tools: Cadence (Virtuoso schematic/Layout editing), Microwind, Chip scope, Modelsim, Xilinx –vivado, Xilinx ISE, Synopsys, MATLAB, LT-Spice, DSCH, Hspice. ... - 2016 Jun 07
Design Project
Lakewood, CA
... Computer Architecture Designed a 32-bit MIPS-based CPU in structural Verilog. Filter Design Analysis and (software) design of Analog and Digital filters. Circuit Network Analysis R, RC, RL, RLC circuits; Diodes, Transistors (BJT, JFET, MOSFET); ... - 2016 May 14
... Computer Architecture Designed a 32-bit MIPS-based CPU in structural Verilog. Filter Design Analysis and (software) design of Analog and Digital filters. Circuit Network Analysis R, RC, RL, RLC circuits; Diodes, Transistors (BJT, JFET, MOSFET); ... - 2016 May 14