Engineer Design
Resume:
Shanshan Xu
Email acbv4y@r.postjobfree.com
SPECIALTY Senior ASIC/FPGA design and pre-silicon/post-silicon
verification
engineer with 15+ years of experience in all
areas of an ASIC/FPGA
design cycle including system/chip-
architecture, block-level micro-
architecture, VHDL/Verolog/SystemVerilog design and
verification,
production testing system design, testing, lab bring-up and
validation.
Expertise in advanced design verification strategies and
methodologies
with demonstrated ability in an indididual contributor and
leadership
roles
EDUCATION Master of Engineering. Cornell University
Major: Electrical Engineering.
B.S., San Jose State University
Major: Electrical Engineering
Minor: Computer Science & Math
EXPERTISE VLSI and FPGA designs
Pre-silicon and Post-silicon
Verifications
Backend design, Synthesis, Timing Closure
DFT, Board Design, System Design
VHDL, Verilogy, SystemVerilog, VerilogAMS
Matlab, UVM, Specman, SystemC
C, C++, Assembly, Perl, TK/TCL, BIOS
Embedded, CPU/GPU, Communication, Video
DSP, PCIE/PCIX/PCI, USB, DDR, ATA, I2C, JTAG
FLASH
PROFESSIONAL EXPERIENCE
4/2013- Current Synapse for HGST/WD
TOE Architecture Consultant and
Verification
(TCP OFFLOADING ENGINE IP with AHB,
DDR3 and MAC
Interface
Architecture/Function/Algorithm/Protocol/Operation
Analysis and Verification and creating missing micro-
architecture documents in cWiki and RTL in SystemVerilog
and
Verification in VHDL and achieving free ASIC bugs
8/2012- 3/2013 Nurotron Biotechnolog Inc.
Sr. Design and Verification Engineer
(Implanted Receiver, Decoder, Neurons Stimulation Controller
Digital Architecture Design and
Verification and achieving 40%
performance improvement with proposed
new embedded-mode
architecture RTL in Verilog and VHDL
(Implanted Receiver, Decoder, Neurons Stimulation FPGA
Implementation and Testing
(Testbench Architecture design and development using
SystemVerilog and UVM library
1/2011- 6/2012 Lattice Semiconductor Mixed Signal Design Group
Staff Design and Verification Engineer
(Architecture and Digital design and implementation for
Temperature Sensor with DSP and ALU
Digital Data Path
using Verilog, System Verilog, UVM
Testbench, Matlab and
Cadence NC-Verilog AMS
(Lattice IP design and verification including 3WIRE, PWM,
TOPLEVEL System Interfaces for Power
Management SoC
04/1997 - 10/2009 Intel Corporation
Sr. Component Design and Verification Engineer
(EGL CPU Unore (10 cores model) Synthesis, Capacity and
Performance Tuning in Eve's Agility Tool
(Falcon Emulation Verific VHDL VFE and Techmap
Synthesis Tool testing
(Falcon Emulation Performance Improvement
(LRB GPU RTL (SystemVerilog) changes for emulation,
capacity
tuning, and vector Simulation (save several
millions for Intel)
(LRB GPU Cache Gate Level simulation for
A0 tapeout by using
Specman and SystemVerilog
(LRB GPU falcon emulation synthesis
(Implement Capacity Tuning scripts in Perl
Communication Research Lab (06/2004-06/2007)
(Configurable and flexible PHY for WIFI, WIMAX and DVB-H
(Scalable Communication Core Adaption Layer Micro
Architecture and digital Design and Verification
(Scalable Communication Core Scrambler Design and
Verification
(Scalable Communication Core Interleaver and De-interleaver
Micro-codes programming in Matlab and C
(Convert a Major design from Verilog to SystemC by using
Verilator Tool Flow
(802.3 GCM mode security vector generator, Micro-
architecture and RTL coding.
(Implement 802.3 GCM mode security vector generator, Micro-
architecture and RTL coding.
(Flexible MAC 802.3, 802.11 & 802.16 MAC Micro Architecture
and digital Design and Verification
(802.16 MAC Micro Architecture and digital Design and
Implement into Altera FPGA
Lan Access Division (04/2001-06/2004)
(Convert a 32bits Single Port Gigabit ASIC into Xilinx FPGA
using Certify Synthesis and Xilinx Ise Tools.
(10G and 1G speeds MAC filter Micro Architecture
Design and
RTL coding and Validation in Verilog
(TOE (TCP/IP OFF LOADING ENGINE) with PCIE/PCIX/PCI
and DDR interfaces Pre-silicon Validation by using
Specman
with coverage and assertion
(Single Port Gigabit Ethernet Chip Synthesis, Static Timing
Analysis and Convergence and Chip Formal Verification
(TOE Verilog RTL coding
(TOE Micro Architecture Design
(Gigabit Ethernet Chip Clock Synchronization Verification on
Mobile System Platform
(Dual Ports Gigabit Ethernet Chip Post Silicon Validation
(Single Port and Dual Ports Gigabit Ethernet Chip
Synthesis,
Static Timing Analysis and Convergence by using Synopsis
Tools
and develop Perl scripts for Synthesis process automation
MicroComputer Research Lab (04/1999-04/2001)
(Blutooth technology research and application on Mobile PC
(Mobile based PC HW design, software & BIOS development
(Develop F-Bridge Platform system by
VHDL RTL coding and
Implement into ORCA FPGA
(Develop mechanical and electrical hardware for 40Khz
omnidirectional E-Pen
(Assist TDE to launch Dell motherboard manufacturing
product
line testing in China
Motherboard Manufacturing Testing (04/1997-04/1999)
(Develop PCI IOC Card for ESG and DPG ISA less motherboard
manufacturing Test system using VHDL RTL coding and
Implement into ORCA FPGA
(Develop 1394 Tester by VHDL RTL coding and Implement into
ORCA FPGA
(Develop ATA33 SSD Hard Drive using VHDL RTL coding
and Implement into ORCA FPGA and develop testing software in
C++
07/96-04/97 Alta Group of Cadence Systems, Inc.
Sr. Design and Verification Engineer
(Develop Color Processor Interface ASIC
with USB and ECP I/O by Verilog RTL coding and Implement
into Altera FPGA and ASIC
(Develop PCI Bus based test system for MPEG2
010/89-06/96 Hewlett-Packard Corporation
Sr. Design and Verification Engineer
(Develop Laser Printer IP ASIC design DMA, ENGIN
Interface,
Front Panel interface using VHDL and RTL coding
(FPGA platform Architecture design and implement for
Laser
Printer 3 models using Altera and Xilinx FPGA Platforms
(Develop Pre-silicon testbench
(Develop Post-silicon validation platforms including board
design
and Automation Controller software in
C
MASTER'S PROJECTS
Develop RLE 1D compression for Image Processing Class
Design and implement a microprocessor implemented into Altera
FPGAs
Develop ISA Bus based Scanner Interface
Implement a simplified and incremented compiler embedded with
a language sensitive editor
Implement Multi Media Thread Implementation using C in
Unix for OS/2 Operating System Class
VLSI layout for Introduction to VLSI Systems Class
Analyze and compare Computer Performance for Computer
Architecture and Organization Class
(Cache Performance Simulation
Honors A member of Eta Kappa Nu
A member of Phi Beta Kappa
Dean List
SPECIAL SKILLS Speak Chinese
Contact this candidate