Design Engineering

Maliha Nisar **** Parkview #*A Irvine, CA ***** Cell phone: 949-***-**** Email: acd8s2@r.postjobfree.com

Objective: Seeking Internship/ Entry- level job in analog & mixed signal IC domain.

Education:

Master in Electrical Engineering (May 2014) GPA=3.58/4.0

University of Southern California

Bachelor in Electronic Engineering (2012) GPA=4.0/4.0

NED University of Engineering & Technology, Pakistan

Relevant Course work:

Electronics Communication Systems (EE-448), RF Filter Design (EE-541), Microwave & Optical Engineering,

MOS VLSI Circuit Design (EE-477), Mixed Signal Integrated Circuit Design I& II (EE536a & b), VLSI Systems Design

(EE577a).

Currently I am also working on a research project lead by Dr. John Choma which is to improve the reliability of IC designed by

implementing embedded RISC architecture on chip.

Software Skills:

Languages: C/C++, HTML, Assembly (8088 and AVR ATMega8), Verilog(basic)

Packages: Hspice, Cadence, OrCAD, Mentor Graphics, Eagle PCB, MultiSIM, Microwind, LABVIEW, MATLAB

Publication:

“Fully Integrated, Highly Linear, Wideband Low Noise Amplifier in 0.13µm CMOS Technology” published in Wireless

Technology and Applications (ISWTA), 2013 IEEE Symposium. Details of the project are below:

Design and Layout of a highly linear wideband Low Noise Amplifier using 130nm CMOS process:

• A three stage distributed amplifier is designed with cascode gain cells and inductive degeneration.

• Performance achieved is : BW = 0.1G-2.7GHz, Gain = 12 dB, S11=-35dB, 1 dB CP= - 12dBm, IIP3 = 1.7dBm, NF =

4.4 dB and unconditionally stable

Related projects:

Design, Assembling and characterization of wireless receiver:

• Designed and analyzed individual blocks of a wireless receiver i.e. Low noise amplifier, Oscillator, Mixer, Wideband

amplifier

• Assembled all these individual blocks together and achieved the functionality of a wireless receiver.

Achieved specs of the design are: Gain = 30dB, Centre Frequency= 200MHz, BW= 50MHz, 1dB CP= -20dBm

Design of Wideband Transimpedance Amplifier using 65nm CMOS:

• Regulated Cascode and CS gain stage along with modified buffer used to achieve the given specifications.

• Results achieved: Trans-impedance gain > 1.3k Ω, BW (-3dB) = 7.6 GHz, Equivalent input noise current (up to

10GHz) < 1uA, Power dissipation = 15mW

Design of Wideband Feedback Amplifier

• Low power with a gain of 18 dB and BW of 1.8GHz and driving a load of upto 5pF employing feedback technique.

Design of Phase Locked Loop for synthesis of 16X frequency

• Output frequency tuning range: 1.06G – 2.59GHz

• Gain of VCO : 1.36GHz/V and tuning voltage range : 0.1-1.2V

Design of 8 bits, 500M samples/sec segmented current steering Digital to Analog Converter

Active Realization of Inductor on chip

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