Design Engineering

Jason Lee **** S. Augusta Court Cell: (***)

***-****

La Habra, CA90631 Home: (714)

***-****

U.S.A.

Email: ******@*******.***

******@*********.***

Summary

? Leading projects in developing System/PCB/ASIC/FPGA for various

Digital/Mixed-Signal/Analog

applications.

? Highly experienced and knowledgeable in defining Hardware

architecture and partition at different levels.

? Extensive hand-on R&D experiences from concept to product,

including specification, design, integration,

simulation, synthesis, timing analysis, system emulation,

debugging, prototyping, troubleshooting,

reworking, DVT, and production release.

? Work and interface closely with customers to meet requirements.

Education

? University of Southern California Los Angeles, CA

Master of Science, Computer Engineering

? National Cheng-Kung University Taiwan

Bachelor of Science, Electrical Engineering

Skill and Knowledge

? H/W Platform -- PC and Workstation

? OS -- MS Windows, Unix, Sun OS/Solaris, DOS

? EDA Tool -- Mentor Graphics PCB Schematic Capture/Simulation, PADs

PCB Layout Viewer,

OrCad PCB Schematic Capture, Cadence Verilog

tools, Viewlogic Powerview,

Altera/Xilinx FPGA HDL/Schematic, Synplicity,

...

Profession Experiences

ILY Enterprise, Inc. DBA Sansdigital City of Industry, CA

Full time Technical Consultant 2011 - Present

Define Architecture, Review Spec, Write technical design document, RFQ

and Work closely with

Suppliers to elect key components, Schematic capture, PCB layout, BOM,

Test procedure, and Prototype/Pilot run/MP problem solving for high

speed digital, mixed signal, analog designs.

? USB3.0 & eSATA to SATA-6G 1-bay/2-bay RAID controller PCB's

(JMicron/ASMedia/Oxford

chipsets) for 2.5" and 3.5" enclosure models.

? USB3.0, eSATA, 1394B to SATA-3G 1-bay/2-bay RAID controller PCB's

(Micron/Oxford + LSI

chipsets) for 2.5" and 3.5" enclosure models.

? SATA-6G 4/5/8-bay Port Multiplier Backplane PCB's (Silicon

Image/Marvell chipsets) for Tower

models.

? eSATA/USB3.0 to SATA-6G 4/5/8-bay Port Multiplier controller PCB's

with enclosure environment

control/monitor (Temp, Voltage, Fan) and DC to DC converters.

? SAS-12G 4/8/12/16/24-bay Fail-over Backplane PCB's with enclosure

environment control/monitor

(Temp, Voltage, Fan) and DC to DC converters for 2.5" and 3.5"

Tower and Rack-mount models.

? SAS bus SGPIO LED display decode on Xilinx CPLD.

? Single bay low cost NAS/DAS controller PCB (INNMax ARM7 SOC with

256MB SDRAM, 1Gb

Ethernet, USB3.0, and eSATA)

Western Digital, Branded Product Lake Forest, CA

Senior Staff Electronic Design Engineer 2008 -- 2011

Define Architecture, Review Spec, Write technical design document, RFQ

and Work closely with

Suppliers to elect key components, Schematic capture, PCB layout, BOM,

Test procedure, and Prototype/Pilot run/MP problem solving for high

speed digital, mixed signal, analog designs.

? USB2.0 to SATAII controller PCB's (Initio chipset) for Mybook and

Passport.

? PCI-e to USB3.0 x 2 HBA PCB (NEC aka Renesas chipset).

? USB3.0 to SATAII controller PCB's (ASMedia and JMicron chipsets) for

Mybook and Passport.

? Firewire 800 (1394B) to SATAII controller PCB's (Oxford, TI, LSI

chipsets) for Mybook and

Passport Studio.

? 1Gb Ethernet to SATAII x 2 (or SATAII x 1 + PCIe x 1) controller PCB

(APM chipset and DDR2)

for Mybook NAS.

? 1Gb Ethernet x 2 to SATAIII x 4 controller PCB for Sentinel SMB

NAS (Stargate).

. Intel Dual Core Atom 525 + ICH901 chip set

. 1GB DDR3

. Broadcom 1Gb Ethernet PHY

. Winbond super IO

. VGA support

. USB2.0 x 3

. Fail Over power Supply (DC 19V x 2)

. Win 2008 Storage Server with AMI BIOS

. Easy status and configuration LCD front panel

ILY Enterprise, Inc. DBA Sansdigital City of Industry, CA

Full time Technical Consultant 2006 -- 2008

Define Architecture, Review Spec, Write technical design document, RFQ

and Work closely with

Suppliers to elect key components, Schematic capture, PCB layout, BOM,

Test procedure, and Prototype/Pilot run/MP problem solving for high

speed digital, mixed signal, analog designs.

? Responsible for System, PCB H/W architecture/spec definition,

circuit design, simulation, debugging,

troubleshooting, EMI certification, and final integration with

F/W and Mechnical enclosure design.

? Various RAID controllers used in external storage enclosures for

performance and file backup

with multiple SATA Hard Drives. Host interfaces include USB2.0,

eSATA, Firewire 400/800

(IEEE-1394A/B), Chip sets include Silicon Image, Oxford

Semi, JMicron, TI, LSI, Microchips,

National Semi, Atmel, SST, ...

? Multiple target DVD/CD/SATA HD/USB Thumb Drive duplicator controller

to support stand alone

high speed copying from an IDE master DVD/CD/HD to multiple target

DVD/CD/ SATA HD/USB

Thumb Drives. A 32-bit microprocessor with a high pin count FPGA

and SDRAM is implemented

to support DMA master SDRAM controller to transfer date between

multiple UDMA IDE interface

channels.

ZAKUS, Inc. (R&D for XAC Automation in Taiwan) Brea, CA

Senior Staff Member 2004 - 2006

? Responsible for System, PCB, ASIC H/W architecture/spec. definition,

circuit design, simulation,

debugging, troubleshooting, and final integration with S/W. RFQ and

Pick key components per cost, performance, and reliability

requirements.

? Applications include POS(Point Of Sale) hand-held wired/wireless

terminal, USB keyboard, Signature

or PIN pad, ... in money transfer/transaction machines for IBM,

Toshiba, FDC, Verifone.

. A 32bit ARM9 controller or 8051 as CPU on PCB with SDRAM, NAND

Flash, Real time clock,

Ethernet, Modem, USB Host/Device/Hub, RS232, ASIC, TFT/STN LCD,

GPRS, Wi-Fi, Power

management/supply, Security, and EMI elimination

. Develop a SOC ASIC containing MSR(Magnetic Stripe Reader),

SCR(Smart Card Reader), RFID

reader, SPI(Serial Port Interface), UART(RS232), USB1.1

Device, Thermal Printer control, DMA,

Interrupt, Compact Flash, Bus timing control, GPIO, ...

functions as core logic in the POS terminal

. Design and build a FPGA platform board to emulate, simulate, and

verify H/W and S/W designs

. Work with H/W, S/W, Q/A teams to meet performance test,

reliability test, EMI test, certification test

Requirements

Altek Lab., Inc. (R&D for Altek Corp. in Taiwan) Gardena, CA

Senior Chief Designer/Director 1998 - 2004

? Responsible for Kodak, Olympus, SONY, Pentax, HP digital camera

million gates SOC architecture

design, defining Spec., block level design and simulation, chip

level integration, timing analysis,

FPGA system level emulation and verification before ASIC tape-out,

debugging, ECO to fix timing

violations for ASIC, system PCB trouble shooting, reworking, system

certifications like USB, EMI,

and production release.

. Five generations SOC ASICs have built-in multiple 32bit ARC

processors and DSPs with some self

defined instructions to accelerate IRP(Image Replication Pipeline)

process (over 25 million

Chips/Cameras shipped in 6 years)

. Design a verification platform PCB's including high speed front

end CCD/CMOS sensor analog and

mixed-signal circuit to verify and test SOC functions and

reliability. These PCB's will be used as

design references for the production PCB's.

. 1~8 millions pixels CCD/CMOS sensors timing generator and

interface

. 12 channels Bus-Master DMA controller with bus arbitration and

SDRAM control

. TFT LCD/TV scaler, timing generator, interface for Video/Audio

clip

. Define and implement algorithms to handle white balance, color

recovery, edge enhancement, anti-

aliasing, filtering, ...

. I2C, SPI, PWM, GPIO, Interrupt, Shutter Control, Motor Control

. Design and integrate TV encoder/decoder, on-chip Boot ROM, Look-Up

table RAM, USB 1.1

Host/Device, JPEG/MPEG compress and decompress, DLL, PLL, ADC, DAC,

Real Time Clock, and

Flash memory interfaces including CF(Compact Flash), MS(Memory

Stick), SD(Security Digital),

MMC, SM(Smart Media)

CMD Technology Inc. Irvine, CA

Principal Design Engineer/Manager 1992 - 1998

? Various digital bus controller ASICs and PCB circuits development.

. DEC Q-bus controller ASIC to replace and enhance glue-logic PCB

to improve performance and

reduce cost

. PCI bus to SCSI controller ASIC

. Several generations PCI bus to IDE controller ASICs (over 20

million Chips/PCBs shipped in 3

years)

. PCI bus to USB1.1 Host controller ASIC

. Low speed USB controller ASIC for keyboard, mouse, joystick

applications

. PCB layout and EMI certification

Printronix Irvine, CA

Senior Design Engineer 1985 - 1991

? Printer controller and Graphics controller PCB development.

. Dot-matrix/Thermal/Laser printer controller boards.

. IGP(Intelligent Graphics Processor) board based on Z180 and

Xilinx FPGA for bar code printing

application on impact, thermal, and laser printers.

. Dot plucker ASIC to control hammers firing in high speed impact

printers

. Coax/Twinax board based on 80186 and PALs to implement IBM mini

computer interface protocols

Excellon Automation Torrance, CA

Design/Test Engineer 1983 - 1985

? A team member responsible for PCB drilling machine spindle

controller board and PCB artwork film

laser pattern generator controller board.

. Design test logic using TTL and write a test code to emulate a

drilling machine system to test the

spindle controller board

. Debug and test Signetics 8X305 bit-slice processor based PCB film

laser pattern generator board

Achievements

? Employee of the year 1992 in CMD Technology

1st Q-bus to SCSI controller ASIC designed and shipped

successfully.

? Employee of the year 1996 in CMD Technology

Multiple design wins on PCI to IDE controller chip and controller

card to be populated on Intel, Asus,

Elite, FIC, Compal, LiteOn PC mother boards to boost company

yearly revenue from US$15M to

US$50M.

? Employee of the year 2002 in Altek

Design wins from Kodak, HP, Polaroid, AGFA to generate company

yearly revenue from US$0 to

US$500M in four years; and contribute to the company IPO at the end

of 2002.

Personal

? U.S. Citizen

? Fluent in both written and spoken English and Chinese

? Able to work independently or seamlessly with team members in

projects

References Available upon request

Contact this candidate