Manager Engineer

Itsik Yomorta

Technical Leader HW&FPGA Design - Omnitron Systems

Irvine, CA

acsrrb@r.postjobfree.com - 949-***-****

20+ years experience in digital and analog design supporting commercial product development. Have participated in all phases of the development cycle as manager, system architect, technical lead and implementer. Wide range of expertise includes high-speed communications, storage systems and interfaces, embedded processors, FPGA/ASIC designs and HW&SW integration/debug.

* Awards/ Publications: 1 issued and 2 pending patents in iStor Networks SKILLS:

FPGA Design: - Altera, Xilinx

VHDL & Verilog for logic entry: - ModelTech, Synplicity, MaxPlus Firmware Design: - C++, C#

ASIC Design - LSI Logic Tools, Toshiba

uProcessor: - i960CA, MPC860, MiniRISC, StrongARM, 80186, Freescale MPC8241/MPC8541 Schematic Capture: - ORCAD, PADS200.

WORK EXPERIENCE

Manager HW Design

Omnitron Systems - Irvine, CA - April 2012 to Present Technical lead and implementation of various FPGA designs(Altera and Xilinx)as well as managing a group of 5 HW engineers designing media converters, Carrier Ethernet demarcation devices, CWDM multiplexers and fiber-optic access products.

Sr. Manager HW Design

Promise Technology - Irvine, CA - July 2010 to March 2012 As iStor was aquired by Promise Technolgy, all the remaining iStor team in Irvine joined the new company, including myself. I am the only HW guy on this group and my responsibilities included design of a new controller, based on the iStor ASIC, to fit into the existing line of RAID controller that Promise had with few additional features:

• New network cards, which also included 2x10GBase-T intefaces.

• SAS interface running at 6Gbps, with the LSI Expander and Controler chips.

• Design of FPGA for interfacing the 2x10G ports to the single 10G port of our ASIC. The fist product is already in latest phase of manufacturing and is planned to ship next month. As can be obvious from the above, my position in Promise Tech is mainly technical, in all the aspects of HW Design, BringUp and Manufacturing and not just as my title suggests(management) Director, ASIC & System Design

iStor Networks - Irvine, CA - March 2002 to July 2010 Recruited by iStor as part of the start-up's initial design team. Started as a Hardware Design Engineer and within 3 years was tasked to manage the Network design of the ASIC as well as the Verification Team. Later was promoted to Director of both the ASIC and the System Design Group, which included up to 7 SW&HW and ASIC design engineers(lately because of my deep knowledge on the Network HW&SW interfaces of the product, I was also tasked to manage 2 SW engineers that were responsible for the uBoot, Linux and Network code of the released product). My duties as both manager and implementer included the following:

• Defined and architected the emulation platform for the highly integrated ASIC which became the heart of all subsequent 10Gb iSCSI Storage Controller products. This emulation platform designated eBlade, partitioned the ASIC functionality into 7 very large XILINX 6000/8000 Series VirtexII FPGAs and was utilized for both ASIC verification and system software development. Designed the complex interconnect scheme for the 7 core FPGAs. The eBlade design also included 9 medium density XILINX FPGAs which served as a diagnostic wrapper around the ASIC emulation core to supply the following functionality: o 1Gb and 10Gb MACs which ran at full speed and acted as Traffic Generators for the emulated ASIC MACs. o Rate conversion of the full-speed external interfaces coupled to the FPGA complex running at 18 MHz. o PCI_X Traffic Generators to stimulate the disk interface portion of the ASIC emulation core logic.

• Definition and design of the MPU used as system host processor.

• Definition of the ASIC Verification Environment and management of the Verification Team for this highly integrated and complex ASIC. This included identification of test cases to be used, ongoing emulation board hardware changes to support corner case testing, network variations and software development during debug and integration of the design.

• Definition and design of a variety of hardware and software tools required for system-level diagnostics and manufacturing test functionality. This included development of the TGIF Traffic Generation Module which permitted the system design team and manufacturing to efficiently test all eight 1Gb EtherNet interfaces or 1 10Gb interface on all iStor products based on the above ASIC.

• Design and bring-up of active backplane to capture and emulate all the corner cases of a fully functional system with 2x 10Gb ports. This backplane was instrumental in supporting the development of the high- availability, dual-redundant iStor controller family. The active backplane was based on the Xilinx Virtex5 series FPGA and was designed using Synopsys simulation tools, ORCAD schematic capture and Synplicity synthesis tools.

• Provided on-site manufacturing support as multiple iStor products were introduced into our off-shore manufacturing facilities (Taiwan and mainland China). Supervised and trained manufacturing engineers and techncians on both the hardware and functional test and diagnostic software suites.

• Definition of the architecture for the dual 10GBase_T capability for the iStor's 10Gb iSCSI controller, design of the HW, FPGA and wrote the control SW to support this product

• Definition and implementation of the necessary changes to the emulation board to support iStor's next generation ASIC (i8010)

Principal Engineer

Gadzoox Networks - Irvine, CA - March 1999 to February 2002 Hardware engineering of Fibre Channel switch products. Later moved to the ASIC group and worked on the design of the next generation switching ASIC. Duties were as follows:

• Definition and architecture of the system.

• System design using Motorola-based CPU and Altera EP20K400E FPGAs using both Verilog and VHDL coding.

• Debugging and integration of the new ASIC, FPGA and firmware with the system.

• Prepared the system for introduction into manufacturing.

• Verilog design and simulation of IBM-based ASIC

Hardware Engineering Manager

SMC & Escalate Networks - Irvine, CA - March 1997 to December 1998 Technical management position which started at SMC Networks and at Escalate Networks after acquisition. Was responsible for the following activities:

• Management of the hardware development team of 5 engineers. Primary products consisted of ATM switches, Ethernet adapters and DSL Modems and Routers.

• Design of ATM switch using Intel's StrongARM processor, Altera FPGAs and proprietary chip set for ATM switches from Virata.

Principal Engineer

LSI Logic - February 1996 to March 1997

Hardware engineering for GSM chip of "System-On-A-Chip" products of LSI Logic. Duties included:

• Design of an evaluation platform for both hardware and software including DSP algorithms.

• Development of GSM chip.

• Learning and implementing with MiniRISC of LSI, OAK DSP and Altera FPGAs.

• Designing several blocks of the code for Altera devices utilizing VHDL code. Hardware Engineer and Manager

Nbase & North_Hills & Adacom - February 1989 to December 1995 This was my first company after finishing my university studies. Entered as an engineer and was promoted in subsequent years to manage the hardware design team. The duties included:

• Managed the activities of up to 8 engineers.

• Implementer of both hardware and firmware design for networking products including Ethernet, Token Ring, IBM 5250 and 3270.

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