| Resume alert | Resumes 41 - 50 of 120 |
VLSI Design Engineer
201301, India
... TECHNICAL SKILLS HDL LANGUAGES : VHDL, Verilog, System Verilog, FPGA and CMOS design Flow TECHNOLOGIES : CMOS, FPGA Development Tools : Modelsim and Xilinx ISE Design Suite (RTL designing & simulation), XILINX SPARTAN3 FPGA . EDUCATION Degree ... - 2016 Jun 04
... TECHNICAL SKILLS HDL LANGUAGES : VHDL, Verilog, System Verilog, FPGA and CMOS design Flow TECHNOLOGIES : CMOS, FPGA Development Tools : Modelsim and Xilinx ISE Design Suite (RTL designing & simulation), XILINX SPARTAN3 FPGA . EDUCATION Degree ... - 2016 Jun 04
Engineering Project
New Delhi, DL, 110001, India
... PROJECT Title: An Area-Throughput Efficient FPGA Implementation Of Block Cipher AES Algorithm. Abstract: Data security is an important aspect of data and computer communication and networks. Now a days data has no boundary. Due to networking, data ... - 2016 Jun 02
... PROJECT Title: An Area-Throughput Efficient FPGA Implementation Of Block Cipher AES Algorithm. Abstract: Data security is an important aspect of data and computer communication and networks. Now a days data has no boundary. Due to networking, data ... - 2016 Jun 02
VLSI Design Engineer
201301, India
... com Phone :+91-852******* VLSI Design Engineer Scaling heights of success, targeting mid-level assignments in ASIC/FPGA Designing & Verification with a reputed organization, prefereably in IT / Hardware industry Preferred Location: Bangalore / ... - 2016 May 24
... com Phone :+91-852******* VLSI Design Engineer Scaling heights of success, targeting mid-level assignments in ASIC/FPGA Designing & Verification with a reputed organization, prefereably in IT / Hardware industry Preferred Location: Bangalore / ... - 2016 May 24
Verilog,Vhdl...
New Delhi, DL, 110001, India
... Technical Skills:- Verilog, VHDL, C, C++, LinuX/Perl, FPGA, Schematic Design Entry, SI and Timing Analysis, SystemVerilog. EDUCATIONALCREDENTIALS:- P.G Deploma (VLSI ) 2015 CDAC, Noida,N/A. M.Tech (VLSI Design) 2014 Galgotias University, Gr.Noida,69 ... - 2016 May 23
... Technical Skills:- Verilog, VHDL, C, C++, LinuX/Perl, FPGA, Schematic Design Entry, SI and Timing Analysis, SystemVerilog. EDUCATIONALCREDENTIALS:- P.G Deploma (VLSI ) 2015 CDAC, Noida,N/A. M.Tech (VLSI Design) 2014 Galgotias University, Gr.Noida,69 ... - 2016 May 23
Engineer Project
201301, India
... 2.Project Title: Robotic Arm Implementation using VHDL Programming (B.Tech Project) Tool Used- Xilinx ISE Webpack Software, VHDL Programming, FPGA/CPLD Kit This project deals with the handling of objects in automatic manner from one place to another ... - 2016 May 15
... 2.Project Title: Robotic Arm Implementation using VHDL Programming (B.Tech Project) Tool Used- Xilinx ISE Webpack Software, VHDL Programming, FPGA/CPLD Kit This project deals with the handling of objects in automatic manner from one place to another ... - 2016 May 15
Manager Engineer
Ghaziabad, UP, 201001, India
... Window based application programming in Visual Basic-6, VC++ (MFC) PCB Design, Control ware (FPGA), Firmware, Optics and Mechanical teams. Embedded Linux, Fedora Core-4, Suse 11.1, ubuntu 14.04 VHDL for FPGAs Kaizen (TTML) ORGANISATIONAL EXPERIENCE ... - 2016 May 14
... Window based application programming in Visual Basic-6, VC++ (MFC) PCB Design, Control ware (FPGA), Firmware, Optics and Mechanical teams. Embedded Linux, Fedora Core-4, Suse 11.1, ubuntu 14.04 VHDL for FPGAs Kaizen (TTML) ORGANISATIONAL EXPERIENCE ... - 2016 May 14
VLSI Intern at Tevatron Technologies Pvt Ltd
New Delhi, DL, 110001, India
... Summary: Good Understanding of the ASIC and FPGA Design Flow. Good understanding of RTL coding using Verilog HDL with all coding styles. Good understanding of layered Test benches using System Verilog and UVM. Exposure in using Industry Standard EDA ... - 2016 Apr 04
... Summary: Good Understanding of the ASIC and FPGA Design Flow. Good understanding of RTL coding using Verilog HDL with all coding styles. Good understanding of layered Test benches using System Verilog and UVM. Exposure in using Industry Standard EDA ... - 2016 Apr 04
Project High School
New Delhi, DL, 110001, India
... in VLSI (FPGA Based Digital Circuit) COMPUTER PROFILE: Basic knowledge of computer Internet Surfing HOBBIES: Reading ACADEMIC QUALIFICATION: Pursuing B.Tech (Electronics & Communication) from C.C.S University Meerut Intermediate from cbse board in ... - 2016 Mar 22
... in VLSI (FPGA Based Digital Circuit) COMPUTER PROFILE: Basic knowledge of computer Internet Surfing HOBBIES: Reading ACADEMIC QUALIFICATION: Pursuing B.Tech (Electronics & Communication) from C.C.S University Meerut Intermediate from cbse board in ... - 2016 Mar 22
VLSI Engineer
New Delhi, DL, 110001, India
... Coding was done in VHDL using FPGA Advantage software on the basis of Finite State Machine of TLC developed by us. Simulation results were demonstrated on FPGA Advantage. College Training (Amity School of Engineering and Technology) during June 2009 ... - 2016 Mar 21
... Coding was done in VHDL using FPGA Advantage software on the basis of Finite State Machine of TLC developed by us. Simulation results were demonstrated on FPGA Advantage. College Training (Amity School of Engineering and Technology) during June 2009 ... - 2016 Mar 21
Verification enginer :: System verilog, UVM,Verilog,VHDL,C++,scripting
201301, India
... • Proficient with scripting Language – SHELL Unix • Knowledge of FPGA interfacing and protocols such as- I2C, SPI,ARBITER,SDRAM Controller and UART • Excellent written and verbal communication skills • Proficiency in grasping new technical concepts ... - 2016 Mar 16
... • Proficient with scripting Language – SHELL Unix • Knowledge of FPGA interfacing and protocols such as- I2C, SPI,ARBITER,SDRAM Controller and UART • Excellent written and verbal communication skills • Proficiency in grasping new technical concepts ... - 2016 Mar 16