MADHURAJ

Address: #D**,B block,mashid walli gali, New Ashok nagar, New Delhi.

Mobile No: +91-888*******

Email Id: acuwnh@r.postjobfree.com

OBJECTIVE:-

To work as VLSI design/asic design/verification engineer. PROFESSIONAL QUALIFICATIONS:-

P.G Diploma under the stream of “VLSI ” from CDAC, Noida. Master of Technology (M.Tech) under the stream of “VLSI Design” from Galgotias University, Greater Noida, U.P.

Bachelor of Technology (B.Tech) under the stream of “Electronics & Instrumentation” from Dr.MGR University, Chennai Tamil Nadu.

Diploma in Computer ApplicationfromComputer Electronics &Management Education Centre. Technical Skills:-

Verilog, VHDL, C, C++, LinuX/Perl, FPGA, Schematic Design Entry, SI and Timing Analysis, SystemVerilog.

EDUCATIONALCREDENTIALS:-

P.G Deploma (VLSI ) 2015 CDAC,

Noida,N/A.

M.Tech (VLSI Design) 2014

Galgotias University, Gr.Noida,69.70%.

B.Tech(Electronics & Instrumentation Engineering) 2012. Dr.MGR University, Chennai,71.73%.

Higher Secondary 2005

Jharkhand Academic Council, 55.11%.

Senior Secondary 2002

Central Board of Secondary Education, 54.2%

EXPERIENCE:-

Work 1 year 8 months as a “COMPUTER TEACHER” in “COMPUTER ELECTRONICS & MANAGEMENT EDUCATION CENTRE” from 04/09/2006 to 30/04/2008. PUBLISHED RESEARCH PAPERS:-

Entitled:-“FPGA Implementation of Convolution using Wallace Tree Multiplier”. In IJERT, Volume. 3, Issue. 06, June-2014.

Entitled:-“Design and Simulation of First Order Sigma-Delta Modulator using LT spice Tool”. In IJERA Journal,Volume. 4, Issue. 7, July2014.

PROJECTS:-

1. Project Name -“Random number generator” Organization – CDAC,Noida. Skills used- Verilog.

Description : A system, device or module that creates a sequence of apparently unrelated numbers. The objective of this project is to create random number generator. The random number generator produces a sequence of number which lacks any pattern, i.e. appear random. The many applications of randomness have led to the development of several different methods for generating random data.

2. Project Name (Final Year Project)-“Efficient FPGA Implementation of Convolution.” Organization - Galgotias University- College project. Skills used- VHDL. Description : A direct method of reducing convolution processing time using hardware computing and implementations of discrete linear convolution of two finite length sequences (NXN). This implementation method is realized by simplifying the convolution building blocks. The purpose of this research is to prove the feasibility of an application specific integrated circuit (ASIC) that performs a convolution on an acquired image in real time. 3. Project Name (Final Year Project)-“Weighing system of food transportation gyrocar.”Organization- Dr.MGR University- College project. Skills used- Application of sensors.

Description : The automatic fruit transportation gyro car works in the economic forest, the vehicle carried weighing system could improve its transportation efficiency. The work described in this paper is mainly concerned with the ultrasonic obstacle avoidance system based on GPRS+ARM of the fruit transportation gyro car.

CO-CURRICULAR ACTIVITIES:-

1. Participated in (skit) prakaran11 organized by instrumentation engineering department. 2. Participated in the special camping program held at Thiruverkadu village by N.S.S. PERSONAL DETAILS:-

Date of Birth: 14th August 1987

Father’s Name: Nalini Kant Pandey

Language Known: English, Hindi

Hobbies: Reading fiction and non-fiction books.

Nationality: Indian

Permanent Address: Electric colony, koderma, Jharkhand-825410 DECELERATION:-

I hereby declare that the above-mentioned information is correct up to my knowledge and I bear the responsibility for the correctness of the above-mentioned particulars. Date: 25-02-2016

Place: NOIDA MADHURAJ

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