VLSI Design Engineer

RAMAN KUMAR

Permanent Address: House No – ***, Exhibition Ground, Civil line – 2, Bijnor, UP – 246701

(Current Location – Noida)

Mobile No: +919********* E-mail: *************@*****.***

OBJECTIVE

Dynamic and career oriented engineering professional with hands on experience in designing VLSI integrated circuits and verification. Looking for a responsible position as a VLSI design engineer with a view to utilize and enhance my skills and experience towards professional growth.

CORE COMPETENCIES

Intel accredited VLSI professional.

Extensive knowledge of the design concepts and Very-large-scale integration circuit systems.

Well versed in VHDL, Verilog and System Verilog.

Well verse with DSP, combinational logic and sequential logic circuits.

Creating test cases for verification.

RTL designing.

TECHNICAL SKILLS

HDL LANGUAGES : VHDL, Verilog, System Verilog, FPGA and CMOS design Flow

TECHNOLOGIES : CMOS, FPGA

Development Tools : Modelsim and Xilinx ISE Design Suite (RTL designing & simulation),

XILINX SPARTAN3 FPGA .

EDUCATION

Degree

Institute/Board/University

Year

Marks

B Tech

Veera College of Engineering, Bijnor/UPTU

2012

65.04%

Intermediate

RJP Arya Inter College, Bijnor/UP Board

2007

70.60%

Matriculation

RJP Arya Inter College, Bijnor/UP Board

2005

60.67%

TRAINING

VLSI DESIGN & VERIFICATION AT MULTISOFT SOLUTIONS, NOIDA (2014-2015)

INTRODUCTION TO VLSI (Very Large Scale Integration)

VHDL : Introduction To VHDL, Designing In VHDL, Data Types & Objects In VHDL, Data Flow Modelling, Behavioural Modelling, Structural Modelling, FSM, Shift Registers & Memories.

VERILOG HDL : Introduction To Verilog HDL, Designing In Verilog HDL, Data Types In Verilog HDL, Gate Level Modelling, Data Flow Modelling, Behavioural Modelling, FSM.

SYSTEM VERILOG: System Verilog Introduction, Different data Types, Procedural Statement, Inter Process Communication, Randomization.

CMOS DESIGNING

FPGA DESIGNING

EXPERIENCE

Organization: Sofcon India Pvt Ltd., Noida (2014-2015)

JOB ROLE: VLSI Design Engineer

Responsibility to provide the technical assistance and training of VLSI, FPGA designing and Verification.

Organization: Engineering Technology Incorporated (2013-2014)

JOB ROLE: Industrial Automation Engineer

Responsibility to develop PLC Program, Installation of PLC, HMI, SCADA and variable frequency drives.

PROJECT & SEMINAR REPORT

PROJECT – Advanced microcontroller Bus Architecture AMBA (AMBA AHB)

Synopsis: AHB stands for advanced high performance bus architecture. This project is all about the on chip communication standard for designing high performance microcontroller. The AMBA AHB is for high-performance, high clock frequency system modules, that supports the efficient connection of processors, on-chip memories and off-chip external memory interfaces.

Role: Module development.

PROJECT – UART

Synopsis: UART is one of the most basic asynchronous communication protocols. Also known as RS-232, it transmits bits serially at a mutually agreed speed without providing a clock. The speed is known as the baud rate.

Role: Module development, Analysis and Design.

PROJECT – Memory Designing & Verification

Synopsis: RTL Designing of memory model and creating verification environment.

Role: Module development, Analysis and Design.

PROJECT – Vedic Multiplier

Synopsis: Currently the speed of the multipliers is limited by the speed of the adders used for partial product addition. This problem can be solved by using an 8-bit multiplier using a Vedic Mathematics for generating the partial products. The partial product addition in Vedic multiplier is realized using carry-skip technique. An 8-bit multiplier is realized using a 4-bit multiplier and modified ripple carry adders. In the proposed design we have reduced the number of logic levels, thus reducing the logic delay.

Role: Module development, Analysis and Design.

PROJECT – ALU (Design & Verification)

Synopsis: Programming & Functionality verification of ALU (Simulation tool- Modelsim).

Role: Module development, Analysis and Design.

PERSONAL DETAILS

Date of Birth: 1st Jul, 1990.

Languages known: English and Hindi.

Interests: RTL Designing, Functional Verification, computer works.

Raman Kumar

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