VLSI Engineer

SHWETA SHARMA

Objective:

To contribute greatly to the field of VLSI by deploying the technical and the soft skills that I have mastered during my academic years.

Work Experience:

Working as an intern in Verification team in 3D-IP SEMICONDUCTORS Pvt. Ltd from 25th August 2015 till date.

Worked as an Intern in VIP (Verification Intellectual Property) R&D domain in Cadence Design Systems Limited from 12th October 2011 to 12th October 2012 Total Experience: 1 year 7months

Job Responsibilities in Cadence:

Analyzed the regressions to report environment related issues.

Responsible for the merging of the code changes in the main branch.

Debugging of the issues in SATA.

Dealing with customer issues in SATA.

Job Responsibilities in 3D-IP Semiconductors:

To make the testcases in UFS(Universal Flash Storage).

To make the sequences in UFS(Universal Flash Storage).

To make functional coverage

Currently running the testcases to report errors and debug it too. Technical Skills:

O/S Platforms : Windows, Linux

Languages : C, C++, Verilog, ‘e’, basics of system verilog Standard/Protocol : Basics of AXI,UFS,SAS and SATA protocol Simulators : Cadence® NCSim, Mentor Graphics® Modelsim, Mentor Graphics® Questasim,Xilinx® ISE

Version Control : clearcase

EDA Tool : Cadence® Virtuoso ADE, Encounter® RTL Compiler Methodology : basics of UVM(Universal Verification Methodology) Projects Undertaken in Cadence:

Development of VIP for Cadence proprietary protocol in ‘e’ o Developed Master BFM: It issues READ or WRITE commands to the Slave BFM and sends packed WRITE burst to the DUT.

o Developed Slave BFM: It collects WRITE burst from the DUT and unpacks it. It sends packed READ burst to the DUT in case READ command is issued from the master BFM.

Scoreboard Development for Cadence proprietary protocol in ‘e’ It involved comparison of fields of sent bursts and received bursts. DUT error is issued in case of mismatch between sent burst and received burst.

Work done in SAS and SATA protocol :

SAS protocol:

o Validation of BURST feature and ALIGN feature: It included testing of these features in a group of three and creation of a new test case independently in case of BURST feature to test additional functionality in it which helped in fixing the issue. o Validation of Rate matching feature: It included testing of this feature in a group of two to ensure that logical phy shall insert deletable primitives between dwords if the logical phy’s logical link rate is faster than the connection rate. o Validation of dropping of the phy speed from G3 to G2: It included dropping of phy speed from G3 to G2 on the fly when transmitter training gets failed. It was done solely.

o Worked internally on the issue raised by the customer which included new 12G eVC sent SNW_3 setting _rx with parity error.

SATA protocol:

o Worked internally on the issue raised by the customer: It included analysis of waveform in detail to deal with the issue i.e. SATA eVC failed to recognize comwake burst during OOB.

Projects Undertaken in 3D-IP semiconductors:

Work done in development of UFSHCI(UFS host controller interface)VIP :- o Understanding spec of UFS host controller

o Making of testcases

o Making of sequences

o Making of functional coverage

o Currently running testcases to report errors

Studying of basics of AXI protocol to be used in UFS.

Development of RAM VIP in UVM..

Academic Qualifications:

DEGREE INSTITUTION YEAR %AGE

M.Tech in VLSI Vellore Institute of

Technology, Chennai

2014 to current CGPA-

7.34(upto

third sem.)

B.Tech in

electronics and

communication

Amity School of Engineering &

Technology

2011

69.99

AISSCE CBSE

New Delhi

Lovely Public Sr.Sec. School Delhi-

110092

2007

78.40

AISCE CBSE New

Delhi

Lovely Public Sr. Sec. School, Delhi-

110092

2005

90.80

.

Projects and Training Undertaken in College:

RBL (Research Based Learning) on DESIGN AND VERIFICATION OF AXI3 PROTOCOL using Verilog in Xilinx® ISE during January 2015 to April 2015. In this project I have designed the AXI master and the AXI slave between whom read and write transactions take place. I have taken a specific case i.e. first write will take place and from that address read will take place. I have done functional verification and code coverage of this design using Mentor Graphics® Questasim.

RBL on DESIGN OF LOW POWER ARRAY MULTIPLIER USING NEW HYBRID FULL ADDERS in Cadence® Virtuoso ADE during August 2014 to October 2014. This project included design of a low power 5 5 array multiplier. The hybrid full adders vary in transistor sizing. A major percentage of multiplier partial product bits has been generated by NAND gates instead of AND gates due to which power consumed is reduced and number of transistors required are also reduced.

Project on DESIGN OF TYPE-I DIGIT SERIAL MULTIPLIER using Verilog in Xilinx® ISE during April 2015. It included design of a digit serial multiplier which gives reduced critical path as compared to traditional one. This project was an implementation of an IEEE paper.

Attended one day long workshop on LABVIEW on 25th april 2015. Learnt basics about LABVIEW.

Project on DESIGN OF TRAFFIC LIGHT CONTROLLER using VHDL during September 2010 to November 2010. In this project my team and I designed a traffic light controller for four way junction. Coding was done in VHDL using FPGA Advantage software on the basis of Finite State Machine of TLC developed by us. Simulation results were demonstrated on FPGA Advantage.

College Training (Amity School of Engineering and Technology) during June 2009 -July 2009 on seismic sensor. This was a simple hardware project made to detect vibrations of very low frequency. We demonstrated detection of “scale vibration” as our result.

Attended one week long workshop on “Introduction to Robotics” conducted by “Intelligent Unmanned Robotics Society” in June 2008.

Six weeks Industrial Training at D.M.R.C from 10th June 2010 to 20th July 2010.

. Extra Curricular Activities:

Performed twice at dance stage show in Siri fort auditorium and in Talkatora auditorium in January 2012 and July 2012 under Danceworx association (Danceform – JAZZ).

Performed at a dance stage show in July 2011 in east Delhi under Delhi dancing association. (Danceform – BOLLYWOOD).

Participated in group discussions and debates at college level.

Have a personal blog which consists of Hindi and English poems and articles too. Strengths

Hardworking

Leadership qualities

Positive attitude

Excellent interpersonal and communication skills. Areas of Interest

Digital electronics, verilog

Personal Information:

Date of Birth : 28-11-1989

Permanent Address : S-585, School Block Shakarpur, Delhi 110092

Hobbies : Writing, Dancing, Anchoring.

Languages Known : English and Hindi

Mobile No. : +919*********, +91-995*******

Email id : ***********@*****.***

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