Verification enginer :: System verilog, UVM,Verilog,VHDL,C++,scripting

B.TECH (ELECTRONICS & COMMUNICATION ENGINEERING) + M.TECH DUAL DEGREE(VLSI)

CAREER OBJECTIVE: To pursue a career with an organization having a global vision, which encourages creativity and offers an opportunity to learn and develop both in professional and personal life, wish to use and enhances my knowledge and ability. SUMMARY

• Knowledge of industry standard hardware description languages (HDLs) like Verilog/VHDL as well as Object Oriented Hardware Verification Languages (OO-HVLs) such as SystemVerilog. Experience in industry verification methodologies and standards such as OVM, UVM using assertion based verification & Coverage Based Verification

:

• Knowledge and hands on experience of QuestaSim, ModelSim NCSim & Xilinx ISE toolset.

• Proficient with scripting Language – SHELL Unix

• Knowledge of FPGA interfacing and protocols such as- I2C, SPI,ARBITER,SDRAM Controller and UART

• Excellent written and verbal communication skills

• Proficiency in grasping new technical concepts quickly & utilizing the same in a productive manner.

Company Name: Tevatron Technologies Pvt. Ltd

WORKING EXPERIENCE:

Designation: Design & Verification Engineer

Experience: January 2013 to Till Date

Customer Site: Freescale Semiconductor Inc. (March 2015 – Till date) Job Responsibilities:

• Creating verification environments from scratch, System & Block level Testbench creation, Assertion & coverage based verification

• Designing and implementing various design of digital logic blocks – RTL design, block level verification - proposed by Vendor (Team Role)

• Executed project’s Documentation in form of Reference manual, Datasheet, White papers etc

PALLAVI ATHA

*****-*************@*****.***

Mobile No: +918*********

2.5 + year of Experience

Working as Verification Engineer in Tevatron

Technologies Pvt. Ltd. Noida

(Customer Site: Freescale Semiconductor)

• Imparting training on Verification flow (covering System verilog.UVM) to Team members, Interns, Customers etc. Present during conferences and seminars to provide guidance and education on new products, new tendencies, and market transition.

• Build strong relationship with partners and key system to enhance the communication and relation between the different product creating business leads and opening to new business development

TECHNICAL SKILLS:

• Programming Language: System Verilog,VHDL,Verilog,C,C++,Embedded C

• Simulation & Synthesis :Model Sim, Xilinx Synthesizer,NC-sim, Xilinx I-Sim, Questasim

• Verification methodologies : UVM,OVM

• Tools Used: Cadence, MentorGraphics,Xilinx, Keil, Topview Simulator,PROTEUS

• Scripting Language: Perl, shell

• Documentation Tools : Oxygen Authoring XML,DITA,Adobe Acrobat, Framemaker

• Protocols : UART, I2C,SPI, Arbiter, FIFO,SRAM,SDRAM Controller.

• Others : FPGA(Spartan3E), Board level design & debugging.

• Application software: MS Office, Photoshop, Corel Draw,Inkscape INDUSTRIAL PROJECTS:

Project 1:

Verification of I2C Protocol using System Verilog (UVM 1.1) Project 2:

Verification of “SDRAM Controller” using System Verilog Project 3:

Verification of SPI Protocol using System Verilog (UVM 1.1) Project 4:

Design & Verification of Arbiter Protocol

Project 5:

Design & Verification of SRAM and FIFO

Project 5:

Designing of UART Protocol using VHDL

Mtech Thesis Project

Designing & Interfacing various design (Seven segment,LCD,PS2 Keyboard,RS-232) in FPGA board (Digilent & Basys – Spartan 3E )

: Design & Implementation of AES Algorithm over FPGA using VHDL & Verilog.(Team size 1)

Microcontroller Based D.T.M.F.Switching Device.(Team Size-3)

• “Design & Implementation of AES Algorithm over FPGA using VHDL” in International Association of Scientific Innovation and research (IJEBEA 13-215) PAPER PUBLISHED:

PRACTICAL TRAINING:-

• 6 Month Industrial Internship on “VLSI Design And Verification” From Tevatron Technologies Pvt Ltd Noida in 2013

• 2 Month training on “CONTROL SYSTEMS (PLC & DCS) & INDUSTRIAL COMMUNICATION PROTOCOLS” from L&T Baroda, Gujarat in 2012.

• 6 week training on PLC from IOCL Gujarat in 2011.

• Embedded system & 8051 microcontroller from Ducat Jaipur in 2011. EDUCATIONAL QUALIFICATION:

Degree Board/University Institute Year Result

M.TECH(dual)

VLSI

Suresh Gyan Vihar

University

Gyan Vihar School

of Engineering.

Jaipur

2013 76%

B.TECH ECE Suresh Gyan Vihar

University

Gyan Vihar School

of Engineering.

Jaipur

2012 76.6%

EXTRA CURICULAR ACTIVITIES:

• Winner in state level chess competition (3 times) & Participated in national level chess competition(2 times)

• Recognized ambassador for IIT Kanpur techfest named TECHKRITI’12

• Member of the organizing committee of AAYAM’12 & AAYAM’11 an international level techfest of our college

• Actively participated in technical & nontechnical competition in our college

• Attended Workshop on Robotics (MNIT jaipur) & Ethical Hacking (IIT Delhi). PERSONAL PROFILE:

Name PALLAVI ATHA

Father’s Name H.S.ATHA

Mother’s Name TINKU ATHA

Date of Birth 25/02/1990

Address 2/14 sector 2 Gujarat refinery township

p.o jawaharnagar,vadodara

Pin Code- 391020

Gujarat

Marital Status Single

Language Known English, Hindi,Bengali,Assamese

Hobbies Playing chess & Sudoku,surfing, cooking,

dancing, making new friends, travelling

DECLARATION:

I here by declare that the above-mentioned information is correct up to my knowledge and I bear the responsibility for the correctness of the above mentioned particulars. PLACE: Noida (PALLAVI ATHA)

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