CURRICULAM VITAE

RAMADEVI KANNURI

Email: acu18u@r.postjobfree.com

Mobile: 789-***-****

PROFESSIONAL OBJECTIVE

To work in an organization where my experience and qualification will be obliged for the benefit of the organization as well as for my career progression with long term association.

SKILL

Comprehensive problem solving abilities accept challenges, have an ability to complete work in given time, power of expression orally as well as on paper.

PROFESSIONAL QUALIFICATION

M.Tech –VLSI System Design in J.B.I.E.T (JNTU affiliated), Andhra Pradesh. Passed- Jan 2011 – percentage marks scored (65%).

B.Tech – ECE (Electronics and Communications Engineering) in Sindhura College of Engineering and Technology(JNTU affiliated), Andhra Pradesh. Passed- May 2007 – percentage marks scored (63.98%).

Diploma (DECE) Govt. Poly. College for Women, Nizamabad (64.45%).

State Board Of School Certificate (SSC) IMSS School Passed-March 1999 with (75.3%).

PROJECT

Title: An Area-Throughput Efficient FPGA Implementation Of Block Cipher AES Algorithm.

Abstract: Data security is an important aspect of data and computer communication and networks. Now a days data has no boundary. Due to networking, data can move from any place to any place at any time. The data is often corrupted, modified and/or lost. Computer and Network security research and development have mainly focused on five to six general security services that encompass the various functions required of an information security facility. In data communication among computers, however, this technique is hardly used. Instead, logical techniques are employed. These techniques include coding methods, spread spectrum and encryption or cryptography and digital signature.

This project addresses design, hardware implementation and performance testing of AES algorithm. An optimized code for the Rijndael algorithm with 128-bit keys has been developed. These area and throughput are carefully trading off to make it suitable for wireless military communication and mobile telephony where emphasis is on the speed as well as on area of implementation.

Role on the project

Wrote and validated functional specification, Prototypes, Design Documents.

Involved in documentation of the project & coding and review process.

Industrial Experience

Worked as an Assistant Professor in AIZZA Engineering College (Telangana) from Nov 2007-Sep 2008 and Sep 2009– Nov 2012.

COMPUTER KNOWLEDGE:

Verilog, VHDL, MATLAB languages.

Microprocessor/Microcontroller programming: 8085, 8086, 8051.

Programming languages: SAP ABAP, Core Java, C, C++.

Operating Systems: WINDOWS 98/2000/XP.

PERSONAL DETAILS

Date of Birth : 28 Aug 1984

Languages known : English, Hindi, Telugu

Marital Status : Married

Address for correspondence : H.No-11, 3thFloor, Aryans Buld, 5thCross, MunishwaraLayout,

Attibele- Bangalore.

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